Messages in this thread | | | Date | Tue, 30 Nov 2021 15:19:58 +0530 | From | Pratyush Yadav <> | Subject | Re: [PATCH] mtd: spi-nor: mt25qu: Ignore 6th ID byte |
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On 25/11/21 08:26AM, Alexander Sverdlin wrote: > Hi Pratyush, > > thanks for the quick reply! > > On 23/11/2021 18:42, Pratyush Yadav wrote: > >> In my opinion, as I look into Micron or Macronix datasheets, write_proto has little to > >> do with erase_proto. (there is currently no separate erase_proto) > > I think this just worked for most flashes since both writes and erases > > generally use 1-bit mode. 4 or 8 bit modes are generally used for reads > > only. > > > >> Before I come up with a totally wrong patch, wanted to ask your opinion, how should > >> it be solved, what do you think? > >> > >> I do not see any erase-related tables for this in JESD216C. > >> I also cannot come up with an example of a chip with erase != 1-1-0. > > See Micron MT35XU512ABA or Cypress S28HS512T (in spansion.c). Both have > > erase in 8D-8D-8D mode. > > > >> Shall I hardcode 1-1-0 for erase? > >> Shall I introduce erase_proto? What would be the logic for its setting/discovery? > > I think introducing erase_proto would be the sensible thing. You would > > have to see if we can discover erase protocol from SFDP. But my question > > is: is that really worth it? Do you really need that little bit speed > > boost you'd get by transmitting write data in 4 bit mode, since the > > large portion of the time would be spent in the chip actually flashing > > the data. > > The problem I have is not speed, but totally not working erase. And I don't want > to downgrade write functionality for other chips.
Then you need to introduce erase_proto.
-- Regards, Pratyush Yadav Texas Instruments Inc.
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