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    Subject[PATCH 4/6] ARM: dts: qcom: sdx55-fn980: Enable PCIe EP
    Date
    Enable PCIe Endpoint controller on the Telit FN980 TLB board based
    on Qualcomm SDX55 platform.

    Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
    ---
    .../boot/dts/qcom-sdx55-telit-fn980-tlb.dts | 46 +++++++++++++++++++
    1 file changed, 46 insertions(+)

    diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts
    index e8b5327afbe7..01ac91738f34 100644
    --- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts
    +++ b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts
    @@ -243,6 +243,14 @@ &pcie0_phy {
    vdda-pll-supply = <&vreg_l4e_bb_0p875>;
    };

    +&pcie_ep {
    + status = "okay";
    +
    + pinctrl-names = "default";
    + pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default
    + &pcie_ep_wake_default>;
    +};
    +
    &qpic_bam {
    status = "ok";
    };
    @@ -267,6 +275,44 @@ &remoteproc_mpss {
    memory-region = <&mpss_adsp_mem>;
    };

    +&tlmm {
    + pcie_ep_clkreq_default: pcie_ep_clkreq_default {
    + mux {
    + pins = "gpio56";
    + function = "pcie_clkreq";
    + };
    + config {
    + pins = "gpio56";
    + drive-strength = <2>;
    + bias-disable;
    + };
    + };
    +
    + pcie_ep_perst_default: pcie_ep_perst_default {
    + mux {
    + pins = "gpio57";
    + function = "gpio";
    + };
    + config {
    + pins = "gpio57";
    + drive-strength = <2>;
    + bias-pull-down;
    + };
    + };
    +
    + pcie_ep_wake_default: pcie_ep_wake_default {
    + mux {
    + pins = "gpio53";
    + function = "gpio";
    + };
    + config {
    + pins = "gpio53";
    + drive-strength = <2>;
    + bias-disable;
    + };
    + };
    +};
    +
    &usb_hsphy {
    status = "okay";
    vdda-pll-supply = <&vreg_l4e_bb_0p875>;
    --
    2.25.1
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