Messages in this thread Patch in this message | | | From | Ajit Kumar Pandey <> | Subject | [PATCH v3 5/7] clk: x86: Fix clk_gate_flags for RV_CLK_GATE | Date | Thu, 25 Nov 2021 11:50:34 +0530 |
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In newer SoC we have to clear bit for disabling 48MHz oscillator clock gate. Remove CLK_GATE_SET_TO_DISABLE flag for proper enable and disable of 48MHz clock.
Signed-off-by: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> --- drivers/clk/x86/clk-fch.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/x86/clk-fch.c b/drivers/clk/x86/clk-fch.c index 4ff2e1b3b3e9..0578297d8322 100644 --- a/drivers/clk/x86/clk-fch.c +++ b/drivers/clk/x86/clk-fch.c @@ -82,7 +82,7 @@ static int fch_clk_probe(struct platform_device *pdev) hws[CLK_GATE_FIXED] = clk_hw_register_gate(NULL, "oscout1", "clk48MHz", 0, fch_data->base + MISCCLKCNTL1, - OSCCLKENB, CLK_GATE_SET_TO_DISABLE, NULL); + OSCCLKENB, 0, NULL); devm_clk_hw_register_clkdev(&pdev->dev, hws[CLK_GATE_FIXED], fch_data->name, NULL); -- 2.25.1
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