Messages in this thread Patch in this message | | | From | Ajit Kumar Pandey <> | Subject | [PATCH v4 7/7] drivers: x86: clk-fch: Add 48MHz fixed clk support on Stoneyridge | Date | Thu, 25 Nov 2021 16:34:47 +0530 |
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Add stoney ridge SOC pci root port id into pci_device_id table to enable 48 MHz fixed fch clock support on Stoneyridge platforms.
Signed-off-by: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> --- drivers/clk/x86/clk-fch.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/clk/x86/clk-fch.c b/drivers/clk/x86/clk-fch.c index 8747212cd289..e3cd176a49e8 100644 --- a/drivers/clk/x86/clk-fch.c +++ b/drivers/clk/x86/clk-fch.c @@ -34,6 +34,7 @@ /* List of supported CPU ids for fixed clk */ #define AMD_CPU_ID_RV 0x15D0 #define AMD_CPU_ID_RN 0x1630 +#define AMD_CPU_ID_ST 0x1576 static const char * const clk_oscout1_parents[] = { "clk48MHz", "clk25MHz" }; static struct clk_hw *hws[ST_MAX_CLKS]; @@ -41,6 +42,7 @@ static struct clk_hw *hws[ST_MAX_CLKS]; static const struct pci_device_id fch_pci_ids[] = { { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) }, + { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_ST) }, { } }; -- 2.25.1
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