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    Subject[RESEND v4 1/6] PCI: imx6: Encapsulate the clock enable into one standalone function
    Date
    No function changes, just encapsulate the i.MX PCIe clocks enable
    operations into one standalone function

    Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
    Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
    ---
    drivers/pci/controller/dwc/pci-imx6.c | 79 ++++++++++++++++-----------
    1 file changed, 48 insertions(+), 31 deletions(-)

    diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
    index fe9842f24093..3bf041314ba7 100644
    --- a/drivers/pci/controller/dwc/pci-imx6.c
    +++ b/drivers/pci/controller/dwc/pci-imx6.c
    @@ -470,38 +470,16 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
    return ret;
    }

    -static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
    -{
    - u32 val;
    - struct device *dev = imx6_pcie->pci->dev;
    -
    - if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr,
    - IOMUXC_GPR22, val,
    - val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED,
    - PHY_PLL_LOCK_WAIT_USLEEP_MAX,
    - PHY_PLL_LOCK_WAIT_TIMEOUT))
    - dev_err(dev, "PCIe PLL lock timeout\n");
    -}
    -
    -static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
    +static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie)
    {
    struct dw_pcie *pci = imx6_pcie->pci;
    struct device *dev = pci->dev;
    int ret;

    - if (imx6_pcie->vpcie && !regulator_is_enabled(imx6_pcie->vpcie)) {
    - ret = regulator_enable(imx6_pcie->vpcie);
    - if (ret) {
    - dev_err(dev, "failed to enable vpcie regulator: %d\n",
    - ret);
    - return;
    - }
    - }
    -
    ret = clk_prepare_enable(imx6_pcie->pcie_phy);
    if (ret) {
    dev_err(dev, "unable to enable pcie_phy clock\n");
    - goto err_pcie_phy;
    + return ret;
    }

    ret = clk_prepare_enable(imx6_pcie->pcie_bus);
    @@ -524,6 +502,51 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)

    /* allow the clocks to stabilize */
    usleep_range(200, 500);
    + return 0;
    +
    +err_ref_clk:
    + clk_disable_unprepare(imx6_pcie->pcie);
    +err_pcie:
    + clk_disable_unprepare(imx6_pcie->pcie_bus);
    +err_pcie_bus:
    + clk_disable_unprepare(imx6_pcie->pcie_phy);
    +
    + return ret;
    +}
    +
    +static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
    +{
    + u32 val;
    + struct device *dev = imx6_pcie->pci->dev;
    +
    + if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr,
    + IOMUXC_GPR22, val,
    + val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED,
    + PHY_PLL_LOCK_WAIT_USLEEP_MAX,
    + PHY_PLL_LOCK_WAIT_TIMEOUT))
    + dev_err(dev, "PCIe PLL lock timeout\n");
    +}
    +
    +static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
    +{
    + struct dw_pcie *pci = imx6_pcie->pci;
    + struct device *dev = pci->dev;
    + int ret;
    +
    + if (imx6_pcie->vpcie && !regulator_is_enabled(imx6_pcie->vpcie)) {
    + ret = regulator_enable(imx6_pcie->vpcie);
    + if (ret) {
    + dev_err(dev, "failed to enable vpcie regulator: %d\n",
    + ret);
    + return;
    + }
    + }
    +
    + ret = imx6_pcie_clk_enable(imx6_pcie);
    + if (ret) {
    + dev_err(dev, "unable to enable pcie clocks\n");
    + goto err_clks;
    + }

    /* Some boards don't have PCIe reset GPIO. */
    if (gpio_is_valid(imx6_pcie->reset_gpio)) {
    @@ -578,13 +601,7 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)

    return;

    -err_ref_clk:
    - clk_disable_unprepare(imx6_pcie->pcie);
    -err_pcie:
    - clk_disable_unprepare(imx6_pcie->pcie_bus);
    -err_pcie_bus:
    - clk_disable_unprepare(imx6_pcie->pcie_phy);
    -err_pcie_phy:
    +err_clks:
    if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) {
    ret = regulator_disable(imx6_pcie->vpcie);
    if (ret)
    --
    2.25.1
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