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    Subject[PATCH v4 3/4] arm64: dts: qcom: sc7280: add edp display dt nodes
    Date
    Add edp controller and phy DT nodes for sc7280.

    Signed-off-by: Krishna Manikandan <quic_mkrishn@quicinc.com>
    Reviewed-by: Stephen Boyd <swboyd@chromium.org>
    Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com>
    ---

    Changes in v4:
    None

    Changes in v3:
    - Add one clock cell per line (Stephen Boyd)
    - Unit address should match first reg property (Stephen Boyd)
    - Remove new line (Stephen Boyd)
    - Add the dsi_phy clocks in dispcc (Kuogee Hsieh)

    Changes in v2:
    - Move regulator definitions to board file (Matthias Kaehlcke)
    - Move the gpio definitions to board file (Matthias Kaehlcke)
    - Move the pinconf to board file (Matthias Kaehlcke)
    - Move status property (Stephen Boyd)
    - Drop flags from interrupts (Stephen Boyd)
    - Add clock names one per line for readability (Stephen Boyd)
    - Rename edp-opp-table (Stephen Boyd)

    arch/arm64/boot/dts/qcom/sc7280.dtsi | 107 ++++++++++++++++++++++++++++++++++-
    1 file changed, 105 insertions(+), 2 deletions(-)

    diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
    index 12c4d32..5ad500e 100644
    --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
    +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
    @@ -2695,8 +2695,8 @@
    <&dsi_phy 1>,
    <0>,
    <0>,
    - <0>,
    - <0>;
    + <&edp_phy 0>,
    + <&edp_phy 1>;
    clock-names = "bi_tcxo",
    "gcc_disp_gpll0_clk",
    "dsi0_phy_pll_out_byteclk",
    @@ -2784,6 +2784,13 @@
    remote-endpoint = <&dsi0_in>;
    };
    };
    +
    + port@1 {
    + reg = <1>;
    + dpu_intf5_out: endpoint {
    + remote-endpoint = <&edp_in>;
    + };
    + };
    };

    mdp_opp_table: opp-table {
    @@ -2899,6 +2906,102 @@

    status = "disabled";
    };
    +
    + msm_edp: edp@aea0000 {
    + compatible = "qcom,sc7280-edp";
    +
    + reg = <0 0xaea0000 0 0x200>,
    + <0 0xaea0200 0 0x200>,
    + <0 0xaea0400 0 0xc00>,
    + <0 0xaea1000 0 0x400>;
    +
    + interrupt-parent = <&mdss>;
    + interrupts = <14>;
    +
    + clocks = <&rpmhcc RPMH_CXO_CLK>,
    + <&gcc GCC_EDP_CLKREF_EN>,
    + <&dispcc DISP_CC_MDSS_AHB_CLK>,
    + <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
    + <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,
    + <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
    + <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;
    + clock-names = "core_xo",
    + "core_ref",
    + "core_iface",
    + "core_aux",
    + "ctrl_link",
    + "ctrl_link_iface",
    + "stream_pixel";
    + #clock-cells = <1>;
    + assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
    + <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
    + assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>;
    +
    + phys = <&edp_phy>;
    + phy-names = "dp";
    +
    + operating-points-v2 = <&edp_opp_table>;
    + power-domains = <&rpmhpd SC7280_CX>;
    +
    + #address-cells = <1>;
    + #size-cells = <0>;
    +
    + status = "disabled";
    +
    + ports {
    + #address-cells = <1>;
    + #size-cells = <0>;
    + port@0 {
    + reg = <0>;
    + edp_in: endpoint {
    + remote-endpoint = <&dpu_intf5_out>;
    + };
    + };
    + };
    +
    + edp_opp_table: opp-table {
    + compatible = "operating-points-v2";
    +
    + opp-160000000 {
    + opp-hz = /bits/ 64 <160000000>;
    + required-opps = <&rpmhpd_opp_low_svs>;
    + };
    +
    + opp-270000000 {
    + opp-hz = /bits/ 64 <270000000>;
    + required-opps = <&rpmhpd_opp_svs>;
    + };
    +
    + opp-540000000 {
    + opp-hz = /bits/ 64 <540000000>;
    + required-opps = <&rpmhpd_opp_nom>;
    + };
    +
    + opp-810000000 {
    + opp-hz = /bits/ 64 <810000000>;
    + required-opps = <&rpmhpd_opp_nom>;
    + };
    + };
    + };
    +
    + edp_phy: phy@aec2a00 {
    + compatible = "qcom,sc7280-edp-phy";
    +
    + reg = <0 0xaec2a00 0 0x19c>,
    + <0 0xaec2200 0 0xa0>,
    + <0 0xaec2600 0 0xa0>,
    + <0 0xaec2000 0 0x1c0>;
    +
    + clocks = <&rpmhcc RPMH_CXO_CLK>,
    + <&gcc GCC_EDP_CLKREF_EN>;
    + clock-names = "aux",
    + "cfg_ahb";
    +
    + #clock-cells = <1>;
    + #phy-cells = <0>;
    +
    + status = "disabled";
    + };
    };

    pdc: interrupt-controller@b220000 {
    --
    2.7.4
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