Messages in this thread Patch in this message | | | From | Taniya Das <> | Subject | [PATCH v1 1/4] clk: qcom: clk-alpha-pll: Increase PLL lock detect poll time | Date | Tue, 2 Nov 2021 15:26:50 +0530 |
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PLL poll for lock detection can take more than 100us for certain type of PLLs, thus update to 200us.
Signed-off-by: Taniya Das <tdas@codeaurora.org> --- drivers/clk/qcom/clk-alpha-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index eaedcce..7cf6cfa 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -204,7 +204,7 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, if (ret) return ret;
- for (count = 100; count > 0; count--) { + for (count = 200; count > 0; count--) { ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); if (ret) return ret; -- Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
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