Messages in this thread | | | Date | Fri, 19 Nov 2021 19:39:01 +0530 | Subject | Re: [PATCHv4 2/2] arm64/io: Add a header for mmio access instrumentation | From | Sai Prakash Ranjan <> |
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On 11/19/2021 7:18 PM, Marc Zyngier wrote: > On Mon, 15 Nov 2021 11:33:30 +0000, > Sai Prakash Ranjan <quic_saipraka@quicinc.com> wrote: >> The new generic header mmio-instrumented.h will keep arch code clean >> and separate from instrumented version which traces mmio register >> accesses. This instrumented header is generic and can be used by other >> architectures as well. Also add a generic flag (__DISABLE_TRACE_MMIO__) >> which is used to disable MMIO tracing in nVHE and if required can be >> used to disable tracing for specific drivers. >> >> Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com> >> --- >> arch/arm64/include/asm/io.h | 25 ++++------- >> arch/arm64/kvm/hyp/nvhe/Makefile | 2 +- >> include/linux/mmio-instrumented.h | 70 +++++++++++++++++++++++++++++++ >> 3 files changed, 80 insertions(+), 17 deletions(-) >> create mode 100644 include/linux/mmio-instrumented.h >> >> diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h >> index 7fd836bea7eb..a635aaaf81b9 100644 >> --- a/arch/arm64/include/asm/io.h >> +++ b/arch/arm64/include/asm/io.h >> @@ -10,6 +10,7 @@ >> >> #include <linux/types.h> >> #include <linux/pgtable.h> >> +#include <linux/mmio-instrumented.h> >> >> #include <asm/byteorder.h> >> #include <asm/barrier.h> >> @@ -21,32 +22,27 @@ >> /* >> * Generic IO read/write. These perform native-endian accesses. >> */ >> -#define __raw_writeb __raw_writeb >> -static inline void __raw_writeb(u8 val, volatile void __iomem *addr) >> +static inline void arch_raw_writeb(u8 val, volatile void __iomem *addr) >> { >> asm volatile("strb %w0, [%1]" : : "rZ" (val), "r" (addr)); >> } >> >> -#define __raw_writew __raw_writew >> -static inline void __raw_writew(u16 val, volatile void __iomem *addr) >> +static inline void arch_raw_writew(u16 val, volatile void __iomem *addr) >> { >> asm volatile("strh %w0, [%1]" : : "rZ" (val), "r" (addr)); >> } >> >> -#define __raw_writel __raw_writel >> -static __always_inline void __raw_writel(u32 val, volatile void __iomem *addr) >> +static __always_inline void arch_raw_writel(u32 val, volatile void __iomem *addr) >> { >> asm volatile("str %w0, [%1]" : : "rZ" (val), "r" (addr)); >> } >> >> -#define __raw_writeq __raw_writeq >> -static inline void __raw_writeq(u64 val, volatile void __iomem *addr) >> +static inline void arch_raw_writeq(u64 val, volatile void __iomem *addr) >> { >> asm volatile("str %x0, [%1]" : : "rZ" (val), "r" (addr)); >> } >> >> -#define __raw_readb __raw_readb >> -static inline u8 __raw_readb(const volatile void __iomem *addr) >> +static inline u8 arch_raw_readb(const volatile void __iomem *addr) >> { >> u8 val; >> asm volatile(ALTERNATIVE("ldrb %w0, [%1]", >> @@ -56,8 +52,7 @@ static inline u8 __raw_readb(const volatile void __iomem *addr) >> return val; >> } >> >> -#define __raw_readw __raw_readw >> -static inline u16 __raw_readw(const volatile void __iomem *addr) >> +static inline u16 arch_raw_readw(const volatile void __iomem *addr) >> { >> u16 val; >> >> @@ -68,8 +63,7 @@ static inline u16 __raw_readw(const volatile void __iomem *addr) >> return val; >> } >> >> -#define __raw_readl __raw_readl >> -static __always_inline u32 __raw_readl(const volatile void __iomem *addr) >> +static __always_inline u32 arch_raw_readl(const volatile void __iomem *addr) >> { >> u32 val; >> asm volatile(ALTERNATIVE("ldr %w0, [%1]", >> @@ -79,8 +73,7 @@ static __always_inline u32 __raw_readl(const volatile void __iomem *addr) >> return val; >> } >> >> -#define __raw_readq __raw_readq >> -static inline u64 __raw_readq(const volatile void __iomem *addr) >> +static inline u64 arch_raw_readq(const volatile void __iomem *addr) >> { >> u64 val; >> asm volatile(ALTERNATIVE("ldr %0, [%1]", >> diff --git a/arch/arm64/kvm/hyp/nvhe/Makefile b/arch/arm64/kvm/hyp/nvhe/Makefile >> index c3c11974fa3b..ff56d2165ea9 100644 >> --- a/arch/arm64/kvm/hyp/nvhe/Makefile >> +++ b/arch/arm64/kvm/hyp/nvhe/Makefile >> @@ -4,7 +4,7 @@ >> # >> >> asflags-y := -D__KVM_NVHE_HYPERVISOR__ -D__DISABLE_EXPORTS >> -ccflags-y := -D__KVM_NVHE_HYPERVISOR__ -D__DISABLE_EXPORTS >> +ccflags-y := -D__KVM_NVHE_HYPERVISOR__ -D__DISABLE_EXPORTS -D__DISABLE_TRACE_MMIO__ >> >> hostprogs := gen-hyprel >> HOST_EXTRACFLAGS += -I$(objtree)/include >> diff --git a/include/linux/mmio-instrumented.h b/include/linux/mmio-instrumented.h >> new file mode 100644 >> index 000000000000..99979c025cc1 >> --- /dev/null >> +++ b/include/linux/mmio-instrumented.h >> @@ -0,0 +1,70 @@ >> +/* SPDX-License-Identifier: GPL-2.0-only */ >> +/* >> + * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. >> + */ >> + >> +#ifndef _LINUX_MMIO_INSTRUMENTED_H >> +#define _LINUX_MMIO_INSTRUMENTED_H >> + >> +#include <linux/tracepoint-defs.h> >> + >> +/* >> + * Tracepoint and MMIO logging symbols should not be visible at EL2(HYP) as >> + * there is no way to execute them and any such MMIO access from EL2 will >> + * explode instantly (Words of Marc Zyngier). So introduce a generic flag >> + * __DISABLE_TRACE_MMIO__ to disable MMIO tracing in nVHE and other drivers >> + * if required. >> + */ > This Gospel would be better placed next to the code that defines the > macro, given that this is an arch-independent include file, and hardly > anyone understands the quirks of a nVHE KVM (and only nVHE, something > that the comment fails to capture). > > M. >
I'll move the comment and include nVHE in the comment as well.
Thanks, Sai
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