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    Subject[PATCH v4 16/25] PCI/ERR: Use PCI_POSSIBLE_ERROR() to check read from hardware
    Date
    An MMIO read from a PCI device that doesn't exist or doesn't respond
    causes a PCI error. There's no real data to return to satisfy the
    CPU read, so most hardware fabricates ~0 data.

    Use PCI_POSSIBLE_ERROR() to check the response we get when we read
    data from hardware.

    This unifies PCI error response checking and make error checks
    consistent and easier to find.

    Signed-off-by: Naveen Naidu <naveennaidu479@gmail.com>
    ---
    drivers/pci/pci.c | 10 +++++-----
    drivers/pci/probe.c | 10 +++++-----
    2 files changed, 10 insertions(+), 10 deletions(-)

    diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
    index 3d2fb394986a..bc82699ed105 100644
    --- a/drivers/pci/pci.c
    +++ b/drivers/pci/pci.c
    @@ -1115,7 +1115,7 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
    return -EIO;

    pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
    - if (pmcsr == (u16) ~0) {
    + if (PCI_POSSIBLE_ERROR(pmcsr)) {
    pci_err(dev, "can't change power state from %s to %s (config space inaccessible)\n",
    pci_power_name(dev->current_state),
    pci_power_name(state));
    @@ -1271,16 +1271,16 @@ static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
    * After reset, the device should not silently discard config
    * requests, but it may still indicate that it needs more time by
    * responding to them with CRS completions. The Root Port will
    - * generally synthesize ~0 data to complete the read (except when
    - * CRS SV is enabled and the read was for the Vendor ID; in that
    - * case it synthesizes 0x0001 data).
    + * generally synthesize ~0 (PCI_ERROR_RESPONSE) data to complete
    + * the read (except when CRS SV is enabled and the read was for the
    + * Vendor ID; in that case it synthesizes 0x0001 data).
    *
    * Wait for the device to return a non-CRS completion. Read the
    * Command register instead of Vendor ID so we don't have to
    * contend with the CRS SV value.
    */
    pci_read_config_dword(dev, PCI_COMMAND, &id);
    - while (id == ~0) {
    + while (PCI_POSSIBLE_ERROR(id)) {
    if (delay > timeout) {
    pci_warn(dev, "not ready %dms after %s; giving up\n",
    delay - 1, reset_type);
    diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
    index 087d3658f75c..c48fe1ab1961 100644
    --- a/drivers/pci/probe.c
    +++ b/drivers/pci/probe.c
    @@ -206,14 +206,14 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
    * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
    * 1 must be clear.
    */
    - if (sz == 0xffffffff)
    + if (PCI_POSSIBLE_ERROR(sz))
    sz = 0;

    /*
    * I don't know how l can have all bits set. Copied from old code.
    * Maybe it fixes a bug on some ancient platform.
    */
    - if (l == 0xffffffff)
    + if (PCI_POSSIBLE_ERROR(l))
    l = 0;

    if (type == pci_bar_unknown) {
    @@ -1683,7 +1683,7 @@ static int pci_cfg_space_size_ext(struct pci_dev *dev)

    if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
    return PCI_CFG_SPACE_SIZE;
    - if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
    + if (PCI_POSSIBLE_ERROR(status) || pci_ext_cfg_is_aliased(dev))
    return PCI_CFG_SPACE_SIZE;

    return PCI_CFG_SPACE_EXP_SIZE;
    @@ -2371,8 +2371,8 @@ bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
    if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
    return false;

    - /* Some broken boards return 0 or ~0 if a slot is empty: */
    - if (*l == 0xffffffff || *l == 0x00000000 ||
    + /* Some broken boards return 0 or ~0 (PCI_ERROR_RESPONSE) if a slot is empty: */
    + if (PCI_POSSIBLE_ERROR(*l) || *l == 0x00000000 ||
    *l == 0x0000ffff || *l == 0xffff0000)
    return false;

    --
    2.25.1
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