Messages in this thread | | | Date | Thu, 18 Nov 2021 10:45:04 +0000 | From | Marc Zyngier <> | Subject | Re: [PATCH] PCI: apple: Reset the port for 100ms on probe |
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On Thu, 18 Nov 2021 10:01:58 +0000, Marc Zyngier <maz@kernel.org> wrote: > > There is also a third delay (Tperst-clk) which represents the time > required for the clock to ramp up before releasing #PERST. No, there > is no value associated with this.
Actually, there is. At least the PCIe CMS r2.0 (2.6.2. AC Specifications) does provide a table of the timings. Tperst-clk has a minimum value of 100us.
Which means I can tighten things further.
M.
-- Without deviation from the norm, progress is not possible.
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