Messages in this thread | | | Date | Wed, 17 Nov 2021 14:47:15 +0100 | From | Herve Codina <> | Subject | Re: [PATCH 2/4] mtd: rawnand: fsmc: Force to use 8 bits access when expected |
| |
Hi,
On Fri, 12 Nov 2021 16:38:59 +0100 Miquel Raynal <miquel.raynal@bootlin.com> wrote:
> Hi Hervé, > > herve.codina@bootlin.com wrote on Fri, 12 Nov 2021 15:38:53 +0100: > > > Some data transfers are expected on 8 bits by the nand core. > > The fsmc driver did not check this constraint and these transfers > > can be done on 32 bits depending on buffer alignment and transfers > > data size. > > > > This patch ensures that these transfers will be 8bits transfers in > > all cases. > > I believe there is a misunderstanding here: NAND buses -between the > NAND controller and the NAND chip- are either 8-bit or 16-bit wide and > the amount of bytes that you will retrieve per register read is not > related to it. > > When the controller supports 16-bit accesses, there are certain > operations that must be performed using only the lowest 8 bits of the > NAND bus, such as reading a status [1]. In this case, the controller > must have a way to disable the 16-bit mode temporarily. See [2] and [3] > for an example. Reading with readb() or readl() will IMHO not impact the > amount of data lines used for the operation. >
Indeed, I misunderstood the force_8bit usage. This patch is not needed and will be simply removed in v2 series.
Thanks, Hervé
| |