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    Subject[PATCH v6 2/8] dt-bindings: phy: Add imx8 pcie phy driver support
    Date
    Add dt-binding for the standalone i.MX8 PCIe PHY driver.

    Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
    Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
    Reviewed-by: Tim Harvey <tharvey@gateworks.com>
    Tested-by: Tim Harvey <tharvey@gateworks.com>
    ---
    .../bindings/phy/fsl,imx8-pcie-phy.yaml | 92 +++++++++++++++++++
    1 file changed, 92 insertions(+)
    create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml

    diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
    new file mode 100644
    index 000000000000..b6421eedece3
    --- /dev/null
    +++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
    @@ -0,0 +1,92 @@
    +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    +%YAML 1.2
    +---
    +$id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
    +$schema: http://devicetree.org/meta-schemas/core.yaml#
    +
    +title: Freescale i.MX8 SoC series PCIe PHY Device Tree Bindings
    +
    +maintainers:
    + - Richard Zhu <hongxing.zhu@nxp.com>
    +
    +properties:
    + "#phy-cells":
    + const: 0
    +
    + compatible:
    + enum:
    + - fsl,imx8mm-pcie-phy
    +
    + reg:
    + maxItems: 1
    +
    + clocks:
    + maxItems: 1
    +
    + clock-names:
    + items:
    + - const: ref
    +
    + resets:
    + maxItems: 1
    +
    + reset-names:
    + items:
    + - const: pciephy
    +
    + fsl,refclk-pad-mode:
    + description: |
    + Specifies the mode of the refclk pad used. It can be UNUSED(PHY
    + refclock is derived from SoC internal source), INPUT(PHY refclock
    + is provided externally via the refclk pad) or OUTPUT(PHY refclock
    + is derived from SoC internal source and provided on the refclk pad).
    + Refer include/dt-bindings/phy/phy-imx8-pcie.h for the constants
    + to be used.
    + $ref: /schemas/types.yaml#/definitions/uint32
    + enum: [ 0, 1, 2 ]
    +
    + fsl,tx-deemph-gen1:
    + description: Gen1 De-emphasis value (optional).
    + $ref: /schemas/types.yaml#/definitions/uint32
    + default: 0
    +
    + fsl,tx-deemph-gen2:
    + description: Gen2 De-emphasis value (optional).
    + $ref: /schemas/types.yaml#/definitions/uint32
    + default: 0
    +
    + fsl,clkreq-unsupported:
    + type: boolean
    + description: A boolean property indicating the CLKREQ# signal is
    + not supported in the board design (optional)
    +
    +required:
    + - "#phy-cells"
    + - compatible
    + - reg
    + - clocks
    + - clock-names
    + - fsl,refclk-pad-mode
    +
    +additionalProperties: false
    +
    +examples:
    + - |
    + #include <dt-bindings/clock/imx8mm-clock.h>
    + #include <dt-bindings/phy/phy-imx8-pcie.h>
    + #include <dt-bindings/reset/imx8mq-reset.h>
    +
    + pcie_phy: pcie-phy@32f00000 {
    + compatible = "fsl,imx8mm-pcie-phy";
    + reg = <0x32f00000 0x10000>;
    + clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
    + clock-names = "ref";
    + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
    + assigned-clock-rates = <100000000>;
    + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
    + resets = <&src IMX8MQ_RESET_PCIEPHY>;
    + reset-names = "pciephy";
    + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
    + #phy-cells = <0>;
    + };
    +...
    --
    2.25.1
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