lkml.org 
[lkml]   [2021]   [Nov]   [17]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
Subjectdrivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn301/dcn301_fpu.c:304:1: warning: the frame size of 1096 bytes is larger than 1024 bytes
tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: ee1703cda8dc777e937dec172da55beaf1a74919
commit: 31484207feb23e6cdb12827560442ab294855923 drm/amd/display: move FPU associated DCN301 code to DML folder
date: 3 weeks ago
config: i386-randconfig-a005-20211117 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
# https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=31484207feb23e6cdb12827560442ab294855923
git remote add linus https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
git fetch --no-tags linus master
git checkout 31484207feb23e6cdb12827560442ab294855923
# save the attached .config to linux build tree
make W=1 ARCH=i386

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn301/dcn301_fpu.c: In function 'dcn301_update_bw_bounding_box':
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn301/dcn301_fpu.c:304:1: warning: the frame size of 1096 bytes is larger than 1024 bytes [-Wframe-larger-than=]
304 | }
| ^


vim +304 drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn301/dcn301_fpu.c

247
248 void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
249 {
250 struct dcn301_resource_pool *pool = TO_DCN301_RES_POOL(dc->res_pool);
251 struct clk_limit_table *clk_table = &bw_params->clk_table;
252 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
253 unsigned int i, closest_clk_lvl;
254 int j;
255
256 dc_assert_fp_enabled();
257
258 /* Default clock levels are used for diags, which may lead to overclocking. */
259 if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
260 dcn3_01_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
261 dcn3_01_ip.max_num_dpp = pool->base.pipe_count;
262 dcn3_01_soc.num_chans = bw_params->num_channels;
263
264 ASSERT(clk_table->num_entries);
265 for (i = 0; i < clk_table->num_entries; i++) {
266 /* loop backwards*/
267 for (closest_clk_lvl = 0, j = dcn3_01_soc.num_states - 1; j >= 0; j--) {
268 if ((unsigned int) dcn3_01_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
269 closest_clk_lvl = j;
270 break;
271 }
272 }
273
274 clock_limits[i].state = i;
275 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
276 clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
277 clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
278 clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
279
280 clock_limits[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
281 clock_limits[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
282 clock_limits[i].dram_bw_per_chan_gbps = dcn3_01_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
283 clock_limits[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
284 clock_limits[i].dtbclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
285 clock_limits[i].phyclk_d18_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
286 clock_limits[i].phyclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
287 }
288
289 for (i = 0; i < clk_table->num_entries; i++)
290 dcn3_01_soc.clock_limits[i] = clock_limits[i];
291
292 if (clk_table->num_entries) {
293 dcn3_01_soc.num_states = clk_table->num_entries;
294 /* duplicate last level */
295 dcn3_01_soc.clock_limits[dcn3_01_soc.num_states] = dcn3_01_soc.clock_limits[dcn3_01_soc.num_states - 1];
296 dcn3_01_soc.clock_limits[dcn3_01_soc.num_states].state = dcn3_01_soc.num_states;
297 }
298 }
299
300 dcn3_01_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
301 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
302
303 dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30);
> 304 }
305

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[unhandled content-type:application/gzip]
\
 
 \ /
  Last update: 2021-11-17 22:54    [W:0.034 / U:1.912 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site