Messages in this thread | | | Subject | Re: [PATCH net 1/4] can: m_can: pci: fix incorrect reference clock rate | From | Jarkko Nikula <> | Date | Tue, 16 Nov 2021 09:11:40 +0200 |
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Hi
On 11/15/21 4:48 PM, Jarkko Nikula wrote: > Hi > > On 11/15/21 11:18 AM, Matthias Schiffer wrote: >> When testing the CAN controller on our Ekhart Lake hardware, we >> determined that all communication was running with twice the configured >> bitrate. Changing the reference clock rate from 100MHz to 200MHz fixed >> this. Intel's support has confirmed to us that 200MHz is indeed the >> correct clock rate. >> >> Fixes: cab7ffc0324f ("can: m_can: add PCI glue driver for Intel >> Elkhart Lake") >> Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> >> --- >> drivers/net/can/m_can/m_can_pci.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/net/can/m_can/m_can_pci.c >> b/drivers/net/can/m_can/m_can_pci.c >> index 89cc3d41e952..d3c030a13cbe 100644 >> --- a/drivers/net/can/m_can/m_can_pci.c >> +++ b/drivers/net/can/m_can/m_can_pci.c >> @@ -18,7 +18,7 @@ >> #define M_CAN_PCI_MMIO_BAR 0 >> -#define M_CAN_CLOCK_FREQ_EHL 100000000 >> +#define M_CAN_CLOCK_FREQ_EHL 200000000 >> #define CTL_CSR_INT_CTL_OFFSET 0x508 > I'll double check this from HW people but at quick test on an HW I have > the signals on an oscilloscope were having 1 us shortest cycle (~500 ns > low, ~500 ns high) when testing like below: > > ip link set can0 type can bitrate 1000000 dbitrate 2000000 fd on
I got confirmation the clock to CAN controller is indeed changed from 100 MHz to 200 MHz in release HW & firmware.
I haven't upgraded the FW in a while on our HW so that perhaps explain why I was seeing expected rate :-)
So which one is more appropriate:
Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> or Reviewed-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
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