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    Subject[PATCH 5.14 173/849] PCI: aardvark: Do not unmask unused interrupts
    Date
    From: Pali Rohár <pali@kernel.org>

    commit 1fb95d7d3c7a926b002fe8a6bd27a1cb428b46dc upstream.

    There are lot of undocumented interrupt bits. To prevent unwanted
    spurious interrupts, fix all *_ALL_MASK macros to define all interrupt
    bits, so that driver can properly mask all interrupts, including those
    which are undocumented.

    Link: https://lore.kernel.org/r/20211005180952.6812-8-kabel@kernel.org
    Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver")
    Signed-off-by: Pali Rohár <pali@kernel.org>
    Signed-off-by: Marek Behún <kabel@kernel.org>
    Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Reviewed-by: Marek Behún <kabel@kernel.org>
    Cc: stable@vger.kernel.org
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/pci/controller/pci-aardvark.c | 6 +++---
    1 file changed, 3 insertions(+), 3 deletions(-)

    --- a/drivers/pci/controller/pci-aardvark.c
    +++ b/drivers/pci/controller/pci-aardvark.c
    @@ -106,13 +106,13 @@
    #define PCIE_ISR0_MSI_INT_PENDING BIT(24)
    #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val))
    #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val))
    -#define PCIE_ISR0_ALL_MASK GENMASK(26, 0)
    +#define PCIE_ISR0_ALL_MASK GENMASK(31, 0)
    #define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48)
    #define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C)
    #define PCIE_ISR1_POWER_STATE_CHANGE BIT(4)
    #define PCIE_ISR1_FLUSH BIT(5)
    #define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val))
    -#define PCIE_ISR1_ALL_MASK GENMASK(11, 4)
    +#define PCIE_ISR1_ALL_MASK GENMASK(31, 0)
    #define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50)
    #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
    #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
    @@ -240,7 +240,7 @@ enum {
    #define PCIE_IRQ_MSI_INT2_DET BIT(21)
    #define PCIE_IRQ_RC_DBELL_DET BIT(22)
    #define PCIE_IRQ_EP_STATUS BIT(23)
    -#define PCIE_IRQ_ALL_MASK 0xfff0fb
    +#define PCIE_IRQ_ALL_MASK GENMASK(31, 0)
    #define PCIE_IRQ_ENABLE_INTS_MASK PCIE_IRQ_CORE_INT

    /* Transaction types */

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