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    Subject[PATCH 5.14 646/849] clk: at91: clk-master: fix prescaler logic
    Date
    From: Claudiu Beznea <claudiu.beznea@microchip.com>

    [ Upstream commit 0ef99f8202c5078a72c05af76bfaed2ea4daab19 ]

    When prescaler value read from register is MASTER_PRES_MAX it means
    that the input clock will be divided by 3. Fix the code to reflect
    this.

    Fixes: 7a110b9107ed8 ("clk: at91: clk-master: re-factor master clock")
    Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
    Link: https://lore.kernel.org/r/20211011112719.3951784-11-claudiu.beznea@microchip.com
    Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
    Signed-off-by: Stephen Boyd <sboyd@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/clk/at91/clk-master.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
    index 2e410815a3405..04d0dd8385945 100644
    --- a/drivers/clk/at91/clk-master.c
    +++ b/drivers/clk/at91/clk-master.c
    @@ -309,7 +309,7 @@ static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw,
    spin_unlock_irqrestore(master->lock, flags);

    pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;
    - if (pres == 3 && characteristics->have_div3_pres)
    + if (pres == MASTER_PRES_MAX && characteristics->have_div3_pres)
    pres = 3;
    else
    pres = (1 << pres);
    --
    2.33.0


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