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    Subject[PATCH 5.14 641/849] phy: qcom-snps: Correct the FSEL_MASK
    Date
    From: Sandeep Maheswaram <quic_c_sanm@quicinc.com>

    [ Upstream commit b475bf0ec40a2b13fb32ef62f5706576d5858460 ]

    The FSEL_MASK which selects the refclock is defined incorrectly.
    It should be [4:6] not [5:7]. Due to this incorrect definition, the BIT(7)
    in USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 is reset which keeps PHY analog
    blocks ON during suspend.
    Fix this issue by correctly defining the FSEL_MASK.

    Fixes: 51e8114f80d0 ("phy: qcom-snps: Add SNPS USB PHY driver for QCOM based SOCs")
    Signed-off-by: Sandeep Maheswaram <quic_c_sanm@quicinc.com>
    Link: https://lore.kernel.org/r/1635135575-5668-1-git-send-email-quic_c_sanm@quicinc.com
    Signed-off-by: Vinod Koul <vkoul@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c
    index ae4bac024c7b1..7e61202aa234e 100644
    --- a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c
    +++ b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c
    @@ -33,7 +33,7 @@

    #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54)
    #define RETENABLEN BIT(3)
    -#define FSEL_MASK GENMASK(7, 5)
    +#define FSEL_MASK GENMASK(6, 4)
    #define FSEL_DEFAULT (0x3 << 4)

    #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1 (0x58)
    --
    2.33.0


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