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    Subject[PATCH 5.15 121/917] KVM: arm64: Extract ESR_ELx.EC only
    Date
    From: Mark Rutland <mark.rutland@arm.com>

    commit 8bb084119f1acc2ec55ea085a97231e3ddb30782 upstream.

    Since ARMv8.0 the upper 32 bits of ESR_ELx have been RES0, and recently
    some of the upper bits gained a meaning and can be non-zero. For
    example, when FEAT_LS64 is implemented, ESR_ELx[36:32] contain ISS2,
    which for an ST64BV or ST64BV0 can be non-zero. This can be seen in ARM
    DDI 0487G.b, page D13-3145, section D13.2.37.

    Generally, we must not rely on RES0 bit remaining zero in future, and
    when extracting ESR_ELx.EC we must mask out all other bits.

    All C code uses the ESR_ELx_EC() macro, which masks out the irrelevant
    bits, and therefore no alterations are required to C code to avoid
    consuming irrelevant bits.

    In a couple of places the KVM assembly extracts ESR_ELx.EC using LSR on
    an X register, and so could in theory consume previously RES0 bits. In
    both cases this is for comparison with EC values ESR_ELx_EC_HVC32 and
    ESR_ELx_EC_HVC64, for which the upper bits of ESR_ELx must currently be
    zero, but this could change in future.

    This patch adjusts the KVM vectors to use UBFX rather than LSR to
    extract ESR_ELx.EC, ensuring these are robust to future additions to
    ESR_ELx.

    Cc: stable@vger.kernel.org
    Signed-off-by: Mark Rutland <mark.rutland@arm.com>
    Cc: Alexandru Elisei <alexandru.elisei@arm.com>
    Cc: Catalin Marinas <catalin.marinas@arm.com>
    Cc: James Morse <james.morse@arm.com>
    Cc: Marc Zyngier <maz@kernel.org>
    Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
    Cc: Will Deacon <will@kernel.org>
    Acked-by: Will Deacon <will@kernel.org>
    Signed-off-by: Marc Zyngier <maz@kernel.org>
    Link: https://lore.kernel.org/r/20211103110545.4613-1-mark.rutland@arm.com
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    arch/arm64/include/asm/esr.h | 1 +
    arch/arm64/kvm/hyp/hyp-entry.S | 2 +-
    arch/arm64/kvm/hyp/nvhe/host.S | 2 +-
    3 files changed, 3 insertions(+), 2 deletions(-)

    --- a/arch/arm64/include/asm/esr.h
    +++ b/arch/arm64/include/asm/esr.h
    @@ -68,6 +68,7 @@
    #define ESR_ELx_EC_MAX (0x3F)

    #define ESR_ELx_EC_SHIFT (26)
    +#define ESR_ELx_EC_WIDTH (6)
    #define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT)
    #define ESR_ELx_EC(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)

    --- a/arch/arm64/kvm/hyp/hyp-entry.S
    +++ b/arch/arm64/kvm/hyp/hyp-entry.S
    @@ -44,7 +44,7 @@
    el1_sync: // Guest trapped into EL2

    mrs x0, esr_el2
    - lsr x0, x0, #ESR_ELx_EC_SHIFT
    + ubfx x0, x0, #ESR_ELx_EC_SHIFT, #ESR_ELx_EC_WIDTH
    cmp x0, #ESR_ELx_EC_HVC64
    ccmp x0, #ESR_ELx_EC_HVC32, #4, ne
    b.ne el1_trap
    --- a/arch/arm64/kvm/hyp/nvhe/host.S
    +++ b/arch/arm64/kvm/hyp/nvhe/host.S
    @@ -115,7 +115,7 @@ SYM_FUNC_END(__hyp_do_panic)
    .L__vect_start\@:
    stp x0, x1, [sp, #-16]!
    mrs x0, esr_el2
    - lsr x0, x0, #ESR_ELx_EC_SHIFT
    + ubfx x0, x0, #ESR_ELx_EC_SHIFT, #ESR_ELx_EC_WIDTH
    cmp x0, #ESR_ELx_EC_HVC64
    b.ne __host_exit


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