lkml.org 
[lkml]   [2021]   [Nov]   [15]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH 5.15 907/917] powerpc/32e: Ignore ESR in instruction storage interrupt handler
    Date
    From: Nicholas Piggin <npiggin@gmail.com>

    commit 81291383ffde08b23bce75e7d6b2575ce9d3475c upstream.

    A e5500 machine running a 32-bit kernel sometimes hangs at boot,
    seemingly going into an infinite loop of instruction storage interrupts.

    The ESR (Exception Syndrome Register) has a value of 0x800000 (store)
    when this happens, which is likely set by a previous store. An
    instruction TLB miss interrupt would then leave ESR unchanged, and if no
    PTE exists it calls directly to the instruction storage interrupt
    handler without changing ESR.

    access_error() does not cause a segfault due to a store to a read-only
    vma because is_exec is true. Most subsequent fault handling does not
    check for a write fault on a read-only vma, and might do strange things
    like create a writeable PTE or call page_mkwrite on a read only vma or
    file. It's not clear what happens here to cause the infinite faulting in
    this case, a fault handler failure or low level PTE or TLB handling.

    In any case this can be fixed by having the instruction storage
    interrupt zero regs->dsisr rather than storing the ESR value to it.

    Fixes: a01a3f2ddbcd ("powerpc: remove arguments from fault handler functions")
    Cc: stable@vger.kernel.org # v5.12+
    Reported-by: Jacques de Laval <jacques.delaval@protonmail.com>
    Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
    Tested-by: Jacques de Laval <jacques.delaval@protonmail.com>
    Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
    Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
    Link: https://lore.kernel.org/r/20211028133043.4159501-1-npiggin@gmail.com
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    arch/powerpc/kernel/head_booke.h | 15 ++++++++++++---
    1 file changed, 12 insertions(+), 3 deletions(-)

    --- a/arch/powerpc/kernel/head_booke.h
    +++ b/arch/powerpc/kernel/head_booke.h
    @@ -465,12 +465,21 @@ label:
    bl do_page_fault; \
    b interrupt_return

    +/*
    + * Instruction TLB Error interrupt handlers may call InstructionStorage
    + * directly without clearing ESR, so the ESR at this point may be left over
    + * from a prior interrupt.
    + *
    + * In any case, do_page_fault for BOOK3E does not use ESR and always expects
    + * dsisr to be 0. ESR_DST from a prior store in particular would confuse fault
    + * handling.
    + */
    #define INSTRUCTION_STORAGE_EXCEPTION \
    START_EXCEPTION(InstructionStorage) \
    - NORMAL_EXCEPTION_PROLOG(0x400, INST_STORAGE); \
    - mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \
    + NORMAL_EXCEPTION_PROLOG(0x400, INST_STORAGE); \
    + li r5,0; /* Store 0 in regs->esr (dsisr) */ \
    stw r5,_ESR(r11); \
    - stw r12, _DEAR(r11); /* Pass SRR0 as arg2 */ \
    + stw r12, _DEAR(r11); /* Set regs->dear (dar) to SRR0 */ \
    prepare_transfer_to_handler; \
    bl do_page_fault; \
    b interrupt_return

    \
     
     \ /
      Last update: 2021-11-16 01:43    [W:2.368 / U:0.196 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site