Messages in this thread Patch in this message | | | From | Ravi Bangoria <> | Subject | [RFC] perf/amd/ibs: Move ibs pmus under perf_sw_context | Date | Mon, 15 Nov 2021 15:18:38 +0530 |
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Ideally, a pmu which is present in each hw thread belongs to perf_hw_context, but perf_hw_context has limitation of allowing only one pmu (a core pmu) and thus other hw pmus need to use either sw or invalid context which limits pmu functionalities.
This is not a new problem. It has been raised in the past, for example, Arm big.LITTLE (same for Intel ADL) and s390 had this issue:
Arm: https://lore.kernel.org/lkml/20160425175837.GB3141@leverpostej s390: https://lore.kernel.org/lkml/20160606082124.GA30154@twins.programming.kicks-ass.net
Arm big.LITTLE (followed by Intel ADL) solved this by allowing multiple (heterogeneous) pmus inside perf_hw_context. It makes sense as they are still registering single pmu for each hw thread.
s390 solved it by moving 2nd hw pmu to perf_sw_context, though that 2nd hw pmu is count mode only, i.e. no sampling.
AMD IBS also has similar problem. IBS pmu is present in each hw thread. But because of perf_hw_context restriction, currently it belongs to perf_invalid_context and thus important functionalities like per-task profiling is not possible with IBS pmu. Moving it to perf_sw_context will: - allow per-task monitoring - allow cgroup wise profiling - allow grouping of IBS with other pmu events - disallow multiplexing
Please let me know if I missed any major benefit or drawback of perf_sw_context. I'm also not sure how easy it would be to lift perf_hw_context restriction and start allowing more pmus in it.
Suggestions?
Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com> --- arch/x86/events/amd/ibs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 9739019d4b67..3cedd3f0c364 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -533,7 +533,7 @@ static struct attribute *ibs_op_format_attrs[] = { static struct perf_ibs perf_ibs_fetch = { .pmu = { - .task_ctx_nr = perf_invalid_context, + .task_ctx_nr = perf_sw_context, .event_init = perf_ibs_init, .add = perf_ibs_add, @@ -558,7 +558,7 @@ static struct perf_ibs perf_ibs_fetch = { static struct perf_ibs perf_ibs_op = { .pmu = { - .task_ctx_nr = perf_invalid_context, + .task_ctx_nr = perf_sw_context, .event_init = perf_ibs_init, .add = perf_ibs_add, -- 2.27.0
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