lkml.org 
[lkml]   [2021]   [Nov]   [15]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH 5.15 153/917] PCI: aardvark: Fix support for PCI_ROM_ADDRESS1 on emulated bridge
    Date
    From: Pali Rohár <pali@kernel.org>

    commit 239edf686c14a9ff926dec2f350289ed7adfefe2 upstream.

    This register is exported at address offset 0x30.

    Link: https://lore.kernel.org/r/20211028185659.20329-8-kabel@kernel.org
    Fixes: 8a3ebd8de328 ("PCI: aardvark: Implement emulated root PCI bridge config space")
    Signed-off-by: Pali Rohár <pali@kernel.org>
    Signed-off-by: Marek Behún <kabel@kernel.org>
    Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Cc: stable@vger.kernel.org
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/pci/controller/pci-aardvark.c | 9 +++++++++
    1 file changed, 9 insertions(+)

    --- a/drivers/pci/controller/pci-aardvark.c
    +++ b/drivers/pci/controller/pci-aardvark.c
    @@ -32,6 +32,7 @@
    #define PCIE_CORE_DEV_ID_REG 0x0
    #define PCIE_CORE_CMD_STATUS_REG 0x4
    #define PCIE_CORE_DEV_REV_REG 0x8
    +#define PCIE_CORE_EXP_ROM_BAR_REG 0x30
    #define PCIE_CORE_PCIEXP_CAP 0xc0
    #define PCIE_CORE_ERR_CAPCTL_REG 0x118
    #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
    @@ -813,6 +814,10 @@ advk_pci_bridge_emul_base_conf_read(stru
    *value = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
    return PCI_BRIDGE_EMUL_HANDLED;

    + case PCI_ROM_ADDRESS1:
    + *value = advk_readl(pcie, PCIE_CORE_EXP_ROM_BAR_REG);
    + return PCI_BRIDGE_EMUL_HANDLED;
    +
    case PCI_INTERRUPT_LINE: {
    /*
    * From the whole 32bit register we support reading from HW only
    @@ -845,6 +850,10 @@ advk_pci_bridge_emul_base_conf_write(str
    advk_writel(pcie, new, PCIE_CORE_CMD_STATUS_REG);
    break;

    + case PCI_ROM_ADDRESS1:
    + advk_writel(pcie, new, PCIE_CORE_EXP_ROM_BAR_REG);
    + break;
    +
    case PCI_INTERRUPT_LINE:
    if (mask & (PCI_BRIDGE_CTL_BUS_RESET << 16)) {
    u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG);

    \
     
     \ /
      Last update: 2021-11-16 00:40    [W:2.254 / U:0.032 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site