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    Subject[PATCH 5.15 326/917] perf/x86/intel/uncore: Fix Intel SPR M3UPI event constraints
    Date
    From: Kan Liang <kan.liang@linux.intel.com>

    [ Upstream commit 4034fb207e302cc0b1f304084d379640c1fb1436 ]

    SPR M3UPI have the exact same event constraints as ICX, so add the
    constraints.

    Fixes: 2a8e51eae7c8 ("perf/x86/intel/uncore: Add Sapphire Rapids server M3UPI support")
    Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
    Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
    Link: https://lkml.kernel.org/r/1629991963-102621-8-git-send-email-kan.liang@linux.intel.com
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    arch/x86/events/intel/uncore_snbep.c | 1 +
    1 file changed, 1 insertion(+)

    diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
    index cd53057fd52de..eb2c6cea9d0d5 100644
    --- a/arch/x86/events/intel/uncore_snbep.c
    +++ b/arch/x86/events/intel/uncore_snbep.c
    @@ -5776,6 +5776,7 @@ static struct intel_uncore_type spr_uncore_upi = {
    static struct intel_uncore_type spr_uncore_m3upi = {
    SPR_UNCORE_PCI_COMMON_FORMAT(),
    .name = "m3upi",
    + .constraints = icx_uncore_m3upi_constraints,
    };

    static struct intel_uncore_type spr_uncore_mdf = {
    --
    2.33.0


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