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    Subject[PATCH 5.10 457/575] clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULL
    Date
    From: Claudiu Beznea <claudiu.beznea@microchip.com>

    [ Upstream commit f12d028b743bb6136da60b17228a1b6162886444 ]

    Use DIV_ROUND_CLOSEST_ULL() to avoid any inconsistency b/w the rate
    computed in sam9x60_frac_pll_recalc_rate() and the one computed in
    sam9x60_frac_pll_compute_mul_frac().

    Fixes: 43b1bb4a9b3e1 ("clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs")
    Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
    Link: https://lore.kernel.org/r/20211011112719.3951784-8-claudiu.beznea@microchip.com
    Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
    Signed-off-by: Stephen Boyd <sboyd@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/clk/at91/clk-sam9x60-pll.c | 4 ++--
    1 file changed, 2 insertions(+), 2 deletions(-)

    diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
    index 78f458a7b2ef4..5a9daa3643a72 100644
    --- a/drivers/clk/at91/clk-sam9x60-pll.c
    +++ b/drivers/clk/at91/clk-sam9x60-pll.c
    @@ -71,8 +71,8 @@ static unsigned long sam9x60_frac_pll_recalc_rate(struct clk_hw *hw,
    struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
    struct sam9x60_frac *frac = to_sam9x60_frac(core);

    - return (parent_rate * (frac->mul + 1) +
    - ((u64)parent_rate * frac->frac >> 22));
    + return parent_rate * (frac->mul + 1) +
    + DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22));
    }

    static int sam9x60_frac_pll_prepare(struct clk_hw *hw)
    --
    2.33.0


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