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    SubjectRe: [RFC PATCH v2 3/4] arm64: dts: qcom: sm8150: add DSI display nodes
    On Fri 12 Nov 20:39 CST 2021, Katherine Perez wrote:

    > Add DSI controller and PHY nodes to sm8150.
    >
    > Signed-off-by: Katherine Perez <kaperez@linux.microsoft.com>
    > ---
    > arch/arm64/boot/dts/qcom/sm8150.dtsi | 183 ++++++++++++++++++++++++++-
    > 1 file changed, 179 insertions(+), 4 deletions(-)
    >
    > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
    > index 38dbc39103ba..afa612daefa1 100644
    > --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
    > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
    > @@ -3261,6 +3261,35 @@ camnoc_virt: interconnect@ac00000 {
    > qcom,bcm-voters = <&apps_bcm_voter>;
    > };
    >
    > + dsi_opp_table: dsi-opp-table {

    As this isn't a mmio device, can we please move it outside of /soc as
    well?

    > + compatible = "operating-points-v2";
    > +
    > + opp-19200000 {
    > + opp-hz = /bits/ 64 <19200000>;
    > + required-opps = <&rpmhpd_opp_min_svs>;
    > + };
    > +
    > + opp-180000000 {
    > + opp-hz = /bits/ 64 <180000000>;
    > + required-opps = <&rpmhpd_opp_low_svs>;
    > + };
    > +
    > + opp-275000000 {
    > + opp-hz = /bits/ 64 <275000000>;
    > + required-opps = <&rpmhpd_opp_svs>;
    > + };
    > +
    > + opp-328580000 {
    > + opp-hz = /bits/ 64 <328580000>;
    > + required-opps = <&rpmhpd_opp_svs_l1>;
    > + };
    > +
    > + opp-358000000 {
    > + opp-hz = /bits/ 64 <358000000>;
    > + required-opps = <&rpmhpd_opp_nom>;
    > + };
    > + };
    > +
    > mdss: mdss@ae00000 {
    > compatible = "qcom,sm8150-mdss";
    > reg = <0 0x0ae00000 0 0x1000>;
    > @@ -3351,6 +3380,152 @@ opp-460000000 {
    > };
    > };
    > };
    > +
    > + dsi0: dsi@ae94000 {

    If you change the label to mdss_dsi0: instead, they group nicely with
    the other mdss related nodes in your device's dts.


    Apart from that I think this series looks good.

    Thanks,
    Bjorn

    > + compatible = "qcom,mdss-dsi-ctrl";
    > + reg = <0 0x0ae94000 0 0x400>;
    > + reg-names = "dsi_ctrl";
    > +
    > + interrupt-parent = <&mdss>;
    > + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
    > +
    > + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
    > + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
    > + <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
    > + <&dispcc DISP_CC_MDSS_ESC0_CLK>,
    > + <&dispcc DISP_CC_MDSS_AHB_CLK>,
    > + <&gcc GCC_DISP_HF_AXI_CLK>;
    > + clock-names = "byte",
    > + "byte_intf",
    > + "pixel",
    > + "core",
    > + "iface",
    > + "bus";
    > +
    > + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
    > + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
    > +
    > + operating-points-v2 = <&dsi_opp_table>;
    > + power-domains = <&rpmhpd SM8150_MMCX>;
    > +
    > + phys = <&dsi0_phy>;
    > + phy-names = "dsi";
    > +
    > + status = "disabled";
    > +
    > + #address-cells = <1>;
    > + #size-cells = <0>;
    > +
    > + ports {
    > + #address-cells = <1>;
    > + #size-cells = <0>;
    > +
    > + port@0 {
    > + reg = <0>;
    > + dsi0_in: endpoint {
    > + remote-endpoint = <&dpu_intf1_out>;
    > + };
    > + };
    > +
    > + port@1 {
    > + reg = <1>;
    > + dsi0_out: endpoint {
    > + };
    > + };
    > + };
    > + };
    > +
    > + dsi0_phy: dsi-phy@ae94400 {
    > + compatible = "qcom,dsi-phy-7nm-8150";
    > + reg = <0 0x0ae94400 0 0x200>,
    > + <0 0x0ae94600 0 0x280>,
    > + <0 0x0ae94900 0 0x260>;
    > + reg-names = "dsi_phy",
    > + "dsi_phy_lane",
    > + "dsi_pll";
    > +
    > + #clock-cells = <1>;
    > + #phy-cells = <0>;
    > +
    > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
    > + <&rpmhcc RPMH_CXO_CLK>;
    > + clock-names = "iface", "ref";
    > +
    > + status = "disabled";
    > + };
    > +
    > + dsi1: dsi@ae96000 {
    > + compatible = "qcom,mdss-dsi-ctrl";
    > + reg = <0 0x0ae96000 0 0x400>;
    > + reg-names = "dsi_ctrl";
    > +
    > + interrupt-parent = <&mdss>;
    > + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
    > +
    > + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
    > + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
    > + <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
    > + <&dispcc DISP_CC_MDSS_ESC1_CLK>,
    > + <&dispcc DISP_CC_MDSS_AHB_CLK>,
    > + <&gcc GCC_DISP_HF_AXI_CLK>;
    > + clock-names = "byte",
    > + "byte_intf",
    > + "pixel",
    > + "core",
    > + "iface",
    > + "bus";
    > +
    > + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
    > + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
    > +
    > + operating-points-v2 = <&dsi_opp_table>;
    > + power-domains = <&rpmhpd SM8150_CX>;
    > +
    > + phys = <&dsi1_phy>;
    > + phy-names = "dsi";
    > +
    > + status = "disabled";
    > +
    > + #address-cells = <1>;
    > + #size-cells = <0>;
    > +
    > + ports {
    > + #address-cells = <1>;
    > + #size-cells = <0>;
    > +
    > + port@0 {
    > + reg = <0>;
    > + dsi1_in: endpoint {
    > + remote-endpoint = <&dpu_intf2_out>;
    > + };
    > + };
    > +
    > + port@1 {
    > + reg = <1>;
    > + dsi1_out: endpoint {
    > + };
    > + };
    > + };
    > + };
    > +
    > + dsi1_phy: dsi-phy@ae96400 {
    > + compatible = "qcom,dsi-phy-7nm-8150";
    > + reg = <0 0x0ae96400 0 0x200>,
    > + <0 0x0ae96600 0 0x280>,
    > + <0 0x0ae96900 0 0x260>;
    > + reg-names = "dsi_phy",
    > + "dsi_phy_lane",
    > + "dsi_pll";
    > +
    > + #clock-cells = <1>;
    > + #phy-cells = <0>;
    > +
    > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
    > + <&rpmhcc RPMH_CXO_CLK>;
    > + clock-names = "iface", "ref";
    > +
    > + status = "disabled";
    > + };
    > };
    >
    > dispcc: clock-controller@af00000 {
    > @@ -3359,10 +3534,10 @@ dispcc: clock-controller@af00000 {
    > power-domains = <&rpmhpd SM8150_MMCX>;
    > required-opps = <&rpmhpd_opp_low_svs>;
    > clocks = <&rpmhcc RPMH_CXO_CLK>,
    > - <0>,
    > - <0>,
    > - <0>,
    > - <0>,
    > + <&dsi0_phy 0>,
    > + <&dsi0_phy 1>,
    > + <&dsi1_phy 0>,
    > + <&dsi1_phy 1>,
    > <0>,
    > <0>;
    > clock-names = "bi_tcxo",
    > --
    > 2.31.1
    >

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