Messages in this thread | | | From | Andy Shevchenko <> | Date | Thu, 11 Nov 2021 22:52:06 +0200 | Subject | Re: [RFC PATCH v3 5/7] gpio: gpiolib: Add ngirq member to struct gpio_irq_chip |
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On Thu, Nov 11, 2021 at 12:59 AM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > Number of GPIO IRQ's supported by the chip is not always
supported GPIO IRQs by the chip
> equal to the number of GPIO pins. For example on Renesas RZ/G2L > SoC where it has GPIO0-122 pins but at a give point a maximum > of only 32 GPIO pins can be used as IRQ lines in the IRQC domain. > > This patch adds ngirq member to struct gpio_irq_chip and passes > this as a size to irq_domain_create_hierarchy()/irq_domain_create_simple() > if it is being set in the driver otherwise fallbacks to using ngpio.
...
> gc->irq.domain = irq_domain_create_hierarchy( > gc->irq.parent_domain, > 0, > - gc->ngpio, > + gc->irq.ngirq ? gc->irq.ngirq : gc->ngpio,
You may use ?: instead as it's done somewhere else in this module.
> gc->irq.fwnode, > &gc->irq.child_irq_domain_ops, > gc);
...
> gc->irq.domain = irq_domain_create_simple(fwnode, > - gc->ngpio, > + gc->irq.ngirq ? gc->irq.ngirq : gc->ngpio,
Ditto.
> gc->irq.first, > gc->irq.domain_ops ?: &gpiochip_domain_ops,
(^^^ You see?)
> gc);
...
> + /** > + * @ngirq: > + * > + * The number of GPIO IRQ's handled by this IRQ domain; usually is
handled GPIO IRQs
> + * equal to ngpio
Missed period.
> + */
-- With Best Regards, Andy Shevchenko
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