lkml.org 
[lkml]   [2021]   [Nov]   [10]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH v5 14/22] crypto: qce: core: Add support to initialize interconnect path
    Date
    From: Thara Gopinath <thara.gopinath@linaro.org>

    Crypto engine on certain Snapdragon processors like sm8150, sm8250, sm8350
    etc. requires interconnect path between the engine and memory to be
    explicitly enabled and bandwidth set prior to any operations. Add support
    in the qce core to enable the interconnect path appropriately.

    Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
    Cc: Rob Herring <robh+dt@kernel.org>
    Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
    [Make header file inclusion alphabetical and use devm_of_icc_get()]
    Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
    ---
    drivers/crypto/qce/core.c | 34 +++++++++++++++++++++++++++-------
    drivers/crypto/qce/core.h | 1 +
    2 files changed, 28 insertions(+), 7 deletions(-)

    diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
    index d3780be44a76..89d9c01ba009 100644
    --- a/drivers/crypto/qce/core.c
    +++ b/drivers/crypto/qce/core.c
    @@ -5,6 +5,7 @@

    #include <linux/clk.h>
    #include <linux/dma-mapping.h>
    +#include <linux/interconnect.h>
    #include <linux/interrupt.h>
    #include <linux/module.h>
    #include <linux/mod_devicetable.h>
    @@ -22,6 +23,8 @@
    #define QCE_MAJOR_VERSION5 0x05
    #define QCE_QUEUE_LENGTH 1

    +#define QCE_DEFAULT_MEM_BANDWIDTH 393600
    +
    static const struct qce_algo_ops *qce_ops[] = {
    #ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
    &skcipher_ops,
    @@ -206,21 +209,35 @@ static int qce_crypto_probe(struct platform_device *pdev)
    if (ret < 0)
    return ret;

    + qce->mem_path = devm_of_icc_get(qce->dev, "memory");
    + if (IS_ERR(qce->mem_path))
    + return PTR_ERR(qce->mem_path);
    +
    qce->core = devm_clk_get(qce->dev, "core");
    - if (IS_ERR(qce->core))
    - return PTR_ERR(qce->core);
    + if (IS_ERR(qce->core)) {
    + ret = PTR_ERR(qce->core);
    + goto err;
    + }

    qce->iface = devm_clk_get(qce->dev, "iface");
    - if (IS_ERR(qce->iface))
    - return PTR_ERR(qce->iface);
    + if (IS_ERR(qce->iface)) {
    + ret = PTR_ERR(qce->iface);
    + goto err;
    + }

    qce->bus = devm_clk_get(qce->dev, "bus");
    - if (IS_ERR(qce->bus))
    - return PTR_ERR(qce->bus);
    + if (IS_ERR(qce->bus)) {
    + ret = PTR_ERR(qce->bus);
    + goto err;
    + }
    +
    + ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH);
    + if (ret)
    + goto err;

    ret = clk_prepare_enable(qce->core);
    if (ret)
    - return ret;
    + goto err_mem_path_disable;

    ret = clk_prepare_enable(qce->iface);
    if (ret)
    @@ -260,6 +277,9 @@ static int qce_crypto_probe(struct platform_device *pdev)
    clk_disable_unprepare(qce->iface);
    err_clks_core:
    clk_disable_unprepare(qce->core);
    +err_mem_path_disable:
    + icc_set_bw(qce->mem_path, 0, 0);
    +err:
    return ret;
    }

    diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h
    index 085774cdf641..228fcd69ec51 100644
    --- a/drivers/crypto/qce/core.h
    +++ b/drivers/crypto/qce/core.h
    @@ -35,6 +35,7 @@ struct qce_device {
    void __iomem *base;
    struct device *dev;
    struct clk *core, *iface, *bus;
    + struct icc_path *mem_path;
    struct qce_dma_data dma;
    int burst_size;
    unsigned int pipe_pair_id;
    --
    2.31.1
    \
     
     \ /
      Last update: 2021-11-10 12:02    [W:3.883 / U:0.468 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site