Messages in this thread | | | Date | Mon, 1 Nov 2021 16:47:05 +0300 | From | Nikita Shubin <> | Subject | Re: [PATCH V6] irqchip/sifive-plic: Fixup EOI failed when masked |
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On Mon, 1 Nov 2021 21:17:36 +0800 guoren@kernel.org wrote:
Hi Guo Ren,
Thank you for your patch.
May be it should be applied to stable ?
Tested-by: Nikita Shubin <nikita.shubin@maquefel.me>
> From: Guo Ren <guoren@linux.alibaba.com> > > When using "devm_request_threaded_irq(,,,,IRQF_ONESHOT,,)" in the > driver, only the first interrupt could be handled, and continue irq > is blocked by hw. Because the riscv plic couldn't complete masked irq > source which has been disabled in enable register. The bug was > firstly reported in [1]. > > Here is the description of Interrupt Completion in PLIC spec [2]: > > The PLIC signals it has completed executing an interrupt handler by > writing the interrupt ID it received from the claim to the > claim/complete register. The PLIC does not check whether the > completion ID is the same as the last claim ID for that target. If > the completion ID does not match an interrupt source that is > currently enabled for the target, the ^^ ^^^^^^^^^ ^^^^^^^ > completion is silently ignored. > > [1] > http://lists.infradead.org/pipermail/linux-riscv/2021-July/007441.html > [2] > https://github.com/riscv/riscv-plic-spec/blob/8bc15a35d07c9edf7b5d23fec9728302595ffc4d/riscv-plic.adoc > > Reported-by: Vincent Pelletier <plr.vincent@gmail.com> > Signed-off-by: Guo Ren <guoren@linux.alibaba.com> > Cc: Anup Patel <anup@brainfault.org> > Cc: Thomas Gleixner <tglx@linutronix.de> > Cc: Marc Zyngier <maz@kernel.org> > Cc: Palmer Dabbelt <palmer@dabbelt.com> > Cc: Atish Patra <atish.patra@wdc.com> > Cc: Nikita Shubin <nikita.shubin@maquefel.me> > Cc: incent Pelletier <plr.vincent@gmail.com> > > --- > > Changes since V6: > - Propagate to plic_irq_eoi for all riscv,plic by Nikita Shubin > - Remove thead related codes > > Changes since V5: > - Move back to mask/unmask > - Fixup the problem in eoi callback > - Remove allwinner,sun20i-d1 IRQCHIP_DECLARE > - Rewrite comment log > > Changes since V4: > - Update comment by Anup > > Changes since V3: > - Rename "c9xx" to "c900" > - Add sifive_plic_chip and thead_plic_chip for difference > > Changes since V2: > - Add a separate compatible string "thead,c9xx-plic" > - set irq_mask/unmask of "plic_chip" to NULL and point > irq_enable/disable of "plic_chip" to plic_irq_mask/unmask > - Add a detailed comment block in plic_init() about the > differences in Claim/Completion process of RISC-V PLIC and C9xx > PLIC. > --- > drivers/irqchip/irq-sifive-plic.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/irqchip/irq-sifive-plic.c > b/drivers/irqchip/irq-sifive-plic.c index cf74cfa82045..259065d271ef > 100644 --- a/drivers/irqchip/irq-sifive-plic.c > +++ b/drivers/irqchip/irq-sifive-plic.c > @@ -163,7 +163,13 @@ static void plic_irq_eoi(struct irq_data *d) > { > struct plic_handler *handler = this_cpu_ptr(&plic_handlers); > > - writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); > + if (irqd_irq_masked(d)) { > + plic_irq_unmask(d); > + writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); > + plic_irq_mask(d); > + } else { > + writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); > + } > } > > static struct irq_chip plic_chip = {
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