Messages in this thread | | | Subject | Re: [PATCH v3 4/4] memory: tegra20-emc: Support matching timings by LPDDR2 configuration | From | Dmitry Osipenko <> | Date | Tue, 5 Oct 2021 18:51:38 +0300 |
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04.10.2021 12:09, Krzysztof Kozlowski пишет: >> +static void emc_read_lpddr_sdram_info(struct tegra_emc *emc, >> + unsigned int emem_dev, >> + bool print_out) >> +{ >> + /* these registers are standard for all LPDDR JEDEC memory chips */ >> + emc_read_lpddr_mode_register(emc, emem_dev, 5, &emc->manufacturer_id); >> + emc_read_lpddr_mode_register(emc, emem_dev, 6, &emc->revision_id1); >> + emc_read_lpddr_mode_register(emc, emem_dev, 7, &emc->revision_id2); >> + emc_read_lpddr_mode_register(emc, emem_dev, 8, &emc->basic_conf4.value); > You ignore the return codes but you should not try to load timings in > such case. The DT could (by mistake or on purpose) have values '0' for > the fields you compare. >
Good suggestion. I'll add a flag that will prevent loading timings if there was MRR error, thanks.
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