Messages in this thread | | | From | Geert Uytterhoeven <> | Date | Tue, 5 Oct 2021 16:19:51 +0200 | Subject | Re: [PATCH] clk: renesas: r9a07g044-cpg: Add clock and reset entries for SPI Multi I/O Bus Controller |
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On Tue, Sep 28, 2021 at 3:01 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Add clock and reset entries for SPI Multi I/O Bus Controller. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-clk-for-v5.16.
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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