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Subject[PATCH v2 RESEND 5/5] clk: x86: Fix clk_gate_flags for RV_CLK_GATE
Date
In AMD's SoC we have to clear bit for disabling 48MHz oscillator
clock gate. Remove CLK_GATE_SET_TO_DISABLE flag for proper enable
and disable of 48MHz clock.

Signed-off-by: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
---
drivers/clk/x86/clk-fch.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/x86/clk-fch.c b/drivers/clk/x86/clk-fch.c
index 19a5c8cf1b3f..517061fc771c 100644
--- a/drivers/clk/x86/clk-fch.c
+++ b/drivers/clk/x86/clk-fch.c
@@ -66,7 +66,7 @@ static int fch_clk_probe(struct platform_device *pdev)

hws[CLK_GATE_FIXED] = clk_hw_register_gate(NULL, "oscout1",
"clk48MHz", 0, fch_data->base + MISCCLKCNTL1,
- OSCCLKENB, CLK_GATE_SET_TO_DISABLE, NULL);
+ OSCCLKENB, 0, NULL);

devm_clk_hw_register_clkdev(&pdev->dev, hws[CLK_GATE_FIXED],
fch_data->name, NULL);
--
2.25.1
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