Messages in this thread | | | Date | Fri, 29 Oct 2021 09:15:35 -0500 | Subject | Re: [PATCH v3 05/21] ACPI: CPPC: add cppc enable register function | From | "Limonciello, Mario" <> |
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On 10/29/2021 08:02, Huang Rui wrote: > From: Jinzhou Su <Jinzhou.Su@amd.com> > > Add a new function to enable CPPC feature. This function > will write Continuous Performance Control package > EnableRegister field on the processor. > > CPPC EnableRegister register described in section 8.4.7.1 of ACPI 6.4: > This element is optional. If supported, contains a resource descriptor > with a single Register() descriptor that describes a register to which > OSPM writes a One to enable CPPC on this processor. Before this register > is set, the processor will be controlled by legacy mechanisms (ACPI > Pstates, firmware, etc.). > > This register will be used for AMD processors to enable amd-pstate > function instead of legacy ACPI P-States. > > Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com> > Signed-off-by: Huang Rui <ray.huang@amd.com> > --- > drivers/acpi/cppc_acpi.c | 45 ++++++++++++++++++++++++++++++++++++++++ > include/acpi/cppc_acpi.h | 5 +++++ > 2 files changed, 50 insertions(+) > > diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c > index c9169c221209..2d2297ef5bf9 100644 > --- a/drivers/acpi/cppc_acpi.c > +++ b/drivers/acpi/cppc_acpi.c > @@ -1275,6 +1275,51 @@ int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) > } > EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs); > > +/** > + * cppc_set_enable - Set to enable CPPC on the processor by writing the > + * Continuous Performance Control package EnableRegister feild.
s/feild/field/
> + * @cpu: CPU for which to enable CPPC register. > + * @enable: 0 - disable, 1 - enable CPPC feature on the processor. > + * > + * Return: 0 for success, -ERRNO or -EIO otherwise. > + */ > +int cppc_set_enable(int cpu, bool enable) > +{ > + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); > + struct cpc_register_resource *enable_reg; > + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); > + struct cppc_pcc_data *pcc_ss_data = NULL; > + int ret = -EINVAL; > + > + if (!cpc_desc) { > + pr_debug("No CPC descriptor for CPU:%d\n", cpu); > + return -EINVAL; > + }
Can this actually happen or is just an extra safety check? Don't you block running based on acpi_cpc_valid?
> + > + enable_reg = &cpc_desc->cpc_regs[ENABLE]; > + > + if (CPC_IN_PCC(enable_reg)) { > + > + if (pcc_ss_id < 0) > + return -EIO; > + > + ret = cpc_write(cpu, enable_reg, enable); > + if (ret) > + return ret; > + > + pcc_ss_data = pcc_data[pcc_ss_id]; > + > + down_write(&pcc_ss_data->pcc_lock); > + /* after writing CPC, transfer the ownership of PCC to platfrom */ > + ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE); > + up_write(&pcc_ss_data->pcc_lock); > + return ret; > + } > + > + return cpc_write(cpu, enable_reg, enable); > +} > +EXPORT_SYMBOL_GPL(cppc_set_enable); > + > /** > * cppc_set_perf - Set a CPU's performance controls. > * @cpu: CPU for which to set performance controls. > diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h > index bc159a9b4a73..92b7ea8d8f5e 100644 > --- a/include/acpi/cppc_acpi.h > +++ b/include/acpi/cppc_acpi.h > @@ -138,6 +138,7 @@ extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf); > extern int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf); > extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs); > extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); > +extern int cppc_set_enable(int cpu, bool enable); > extern int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps); > extern bool acpi_cpc_valid(void); > extern int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data); > @@ -162,6 +163,10 @@ static inline int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) > { > return -ENOTSUPP; > } > +static inline int cppc_set_enable(int cpu, bool enable) > +{ > + return -ENOTSUPP; > +} > static inline int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps) > { > return -ENOTSUPP; >
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