Messages in this thread | | | From | David Laight <> | Subject | RE: [PATCH v5 00/15] x86: Add support for Clang CFI | Date | Wed, 27 Oct 2021 21:31:21 +0000 |
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From: Mark Rutland > Sent: 27 October 2021 14:18 > > On Wed, Oct 27, 2021 at 12:55:17PM +0000, David Laight wrote: > > From: Mark Rutland > > > Sent: 27 October 2021 13:05 > > ... > > > Taking a step back, it'd be nicer if we didn't have the jump-table shim > > > at all, and had some SW landing pad (e.g. a NOP with some magic bytes) > > > in the callees that the caller could check for. Then function pointers > > > would remain callable in call cases, and we could explcitly add landing > > > pads to asm to protect those. I *think* that's what the grsecurity folk > > > do, but I could be mistaken. > > > > It doesn't need to be a 'landing pad'. > > The 'magic value' could be at 'label - 8'. > > Sure; I'd intended to mean the general case of something at some fixed > offset from the entrypoint, either before or after, potentially but not > necessarily inline in the executed instruction stream.
What you really want is to be able to read the value using the I-cache so as not to pollute the D-cache with code bytes and to avoid having both an I-cache and D-cache miss at the same time for the same memory.
Even if the I-cache read took an extra clock (or two) I suspect it would be an overall gain. This is also true for code that uses pc-relative instructions to read constants - common in arm-64.
Not sure any hardware lets you do that though :-(
David
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