| Date | Tue, 26 Oct 2021 16:16:40 -0000 | From | "tip-bot2 for Chang S. Bae" <> | Subject | [tip: x86/fpu] x86/msr-index: Add MSRs for XFD |
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The following commit has been merged into the x86/fpu branch of tip:
Commit-ID: dae1bd58389615d401a84aedc38fa075ef8f7de6 Gitweb: https://git.kernel.org/tip/dae1bd58389615d401a84aedc38fa075ef8f7de6 Author: Chang S. Bae <chang.seok.bae@intel.com> AuthorDate: Thu, 21 Oct 2021 15:55:17 -07:00 Committer: Borislav Petkov <bp@suse.de> CommitterDate: Tue, 26 Oct 2021 10:18:09 +02:00
x86/msr-index: Add MSRs for XFD
XFD introduces two MSRs:
- IA32_XFD to enable/disable a feature controlled by XFD
- IA32_XFD_ERR to expose to the #NM trap handler which feature was tried to be used for the first time.
Both use the same xstate-component bitmap format, used by XCR0.
Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20211021225527.10184-14-chang.seok.bae@intel.com --- arch/x86/include/asm/msr-index.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index a7c4134..01e2650 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -625,6 +625,8 @@ #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc +#define MSR_IA32_XFD 0x000001c4 +#define MSR_IA32_XFD_ERR 0x000001c5 #define MSR_IA32_XSS 0x00000da0 #define MSR_IA32_APICBASE 0x0000001b
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