Messages in this thread | | | From | Guo Ren <> | Date | Mon, 25 Oct 2021 14:00:46 +0800 | Subject | Re: [RESEND PATCH V3 1/2] dt-bindings: riscv: add mmu-supports-svpbmt for Svpbmt |
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On Mon, Oct 25, 2021 at 12:17 PM Anup Patel <anup@brainfault.org> wrote: > > On Mon, Oct 25, 2021 at 9:36 AM <wefu@redhat.com> wrote: > > > > From: Wei Fu <wefu@redhat.com> > > > > Previous patch has added svpbmt in arch/riscv and changed the > > DT mmu-type. Update dt-bindings related property here. > > > > Signed-off-by: Wei Fu <wefu@redhat.com> > > Co-developed-by: Guo Ren <guoren@kernel.org> > > Signed-off-by: Guo Ren <guoren@kernel.org> > > Cc: Anup Patel <anup@brainfault.org> > > Cc: Palmer Dabbelt <palmer@dabbelt.com> > > Cc: Rob Herring <robh+dt@kernel.org> > > --- > > Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > > index e534f6a7cfa1..76f324d85e12 100644 > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > @@ -59,6 +59,11 @@ properties: > > - riscv,sv48 > > - riscv,none > > > > + mmu-supports-svpbmt: > > + description: > > + Describes the CPU's mmu-supports-svpbmt support > > + $ref: '/schemas/types.yaml#/definitions/phandle' > > There were various proposals from different folks in the previous > email threads. > > I think most of us were converging on: > 1) Don't modify "mmu-type" DT property for backward > compatibility I agree. FuWei has followed that in the patch.
> 2) Add boolean DT property "riscv,svpmbt" under > "mmu" child DT node of each CPU DT node. Same will apply > to boolean DT property "riscv,svnapot" as well. We have various proposals here: @Philipp suggests firstly, but break the backward compatibility: cpu@0 { ... mmu { type = "riscv,sv39"; supports-svpbmt; supports-svnapot; };
@guoren suggests reusing the mmu-type, but seems not clean. cpu@0 { ... mmu-type = "riscv,sv39,svpbmt,svnapot";
@fuwei suggests simple name property in CPU section: cpu@0 { ... mmu-type = "riscv,sv39"; mmu-supports-svpbmt; mmu-supports-svnapot;
@Anup suggests: cpu@0 { ... mmu-type = "riscv,sv39"; mmu { supports-svpbmt; supports-svnapot; };
Any other suggestions? Thx.
> > We also have bitmanip and vector broken down into smaller > extensions so grouping related extensions as separate DT node > under each CPU node will be more readable and easy to parse. Do you mean combine mmu extensions with them together? cpu@0 { ... extensions { supports-svpbmt; supports-svnapot; supports-bitmanip; supports-vector-v0p7; };
> > Regards, > Anup > > > + > > riscv,isa: > > description: > > Identifies the specific RISC-V instruction set architecture > > -- > > 2.25.4 > >
-- Best Regards Guo Ren
ML: https://lore.kernel.org/linux-csky/
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