lkml.org 
[lkml]   [2021]   [Oct]   [23]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[RFC 11/13] arm64: dts: mt8192: Add apu power nodes
    Date
    Add apu power node.

    Signed-off-by: Flora Fu <flora.fu@mediatek.com>
    ---
    arch/arm64/boot/dts/mediatek/mt8192.dtsi | 62 ++++++++++++++++++++++++
    1 file changed, 62 insertions(+)

    diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
    index d5e417a512a7..c505c6926839 100644
    --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
    +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
    @@ -964,6 +964,68 @@
    };
    };

    + apusys_power: apusys_power@190f1000 {
    + compatible = "mediatek,apusys-power",
    + "mediatek,mt8192-apu-power";
    + reg = <0 0x190f1000 0 0x1000>,
    + <0 0x19000600 0 0x100>;
    + reg-names = "apu_pcu",
    + "apu_spare";
    + power-domains = <&apuspm 0>;
    + clocks = <&topckgen CLK_TOP_DSP_SEL>,
    + <&topckgen CLK_TOP_DSP1_SEL>,
    + <&topckgen CLK_TOP_DSP1_NPUPLL_SEL>,
    + <&topckgen CLK_TOP_DSP2_SEL>,
    + <&topckgen CLK_TOP_DSP2_NPUPLL_SEL>,
    + <&topckgen CLK_TOP_DSP5_SEL>,
    + <&topckgen CLK_TOP_DSP5_APUPLL_SEL>,
    + <&topckgen CLK_TOP_IPU_IF_SEL>,
    + <&clk26m>,
    + <&topckgen CLK_TOP_MAINPLL_D4_D2>,
    + <&topckgen CLK_TOP_UNIVPLL_D4_D2>,
    + <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
    + <&topckgen CLK_TOP_MMPLL_D6>,
    + <&topckgen CLK_TOP_MMPLL_D5>,
    + <&topckgen CLK_TOP_MMPLL_D4>,
    + <&topckgen CLK_TOP_UNIVPLL_D5>,
    + <&topckgen CLK_TOP_UNIVPLL_D4>,
    + <&topckgen CLK_TOP_UNIVPLL_D3>,
    + <&topckgen CLK_TOP_MAINPLL_D6>,
    + <&topckgen CLK_TOP_MAINPLL_D4>,
    + <&topckgen CLK_TOP_MAINPLL_D3>,
    + <&topckgen CLK_TOP_TVDPLL>,
    + <&topckgen CLK_TOP_APUPLL>,
    + <&topckgen CLK_TOP_NPUPLL>,
    + <&apmixedsys CLK_APMIXED_APUPLL>,
    + <&apmixedsys CLK_APMIXED_NPUPLL>;
    + clock-names = "clk_top_dsp_sel",
    + "clk_top_dsp1_sel",
    + "clk_top_dsp1_npupll_sel",
    + "clk_top_dsp2_sel",
    + "clk_top_dsp2_npupll_sel",
    + "clk_top_dsp5_sel",
    + "clk_top_dsp5_apupll_sel",
    + "clk_top_ipu_if_sel",
    + "clk_top_clk26m",
    + "clk_top_mainpll_d4_d2",
    + "clk_top_univpll_d4_d2",
    + "clk_top_univpll_d6_d2",
    + "clk_top_mmpll_d6",
    + "clk_top_mmpll_d5",
    + "clk_top_mmpll_d4",
    + "clk_top_univpll_d5",
    + "clk_top_univpll_d4",
    + "clk_top_univpll_d3",
    + "clk_top_mainpll_d6",
    + "clk_top_mainpll_d4",
    + "clk_top_mainpll_d3",
    + "clk_top_tvdpll_ck",
    + "clk_top_apupll_ck",
    + "clk_top_npupll_ck",
    + "clk_apmixed_apupll_rate",
    + "clk_apmixed_npupll_rate";
    + };
    +
    camsys: clock-controller@1a000000 {
    compatible = "mediatek,mt8192-camsys";
    reg = <0 0x1a000000 0 0x1000>;
    --
    2.18.0
    \
     
     \ /
      Last update: 2021-10-23 13:16    [W:3.776 / U:0.008 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site