Messages in this thread | | | Date | Wed, 20 Oct 2021 17:48:38 +0100 | From | Marc Zyngier <> | Subject | Re: [PATCH V4 1/3] irqchip/sifive-plic: Add thead,c900-plic support |
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On Wed, 20 Oct 2021 17:08:36 +0100, Anup Patel <anup@brainfault.org> wrote: > > On Wed, Oct 20, 2021 at 8:38 PM Marc Zyngier <maz@kernel.org> wrote: > > > > On Wed, 20 Oct 2021 15:33:49 +0100, > > Anup Patel <anup@brainfault.org> wrote: > > > > > > On Wed, Oct 20, 2021 at 7:04 PM Marc Zyngier <maz@kernel.org> wrote: > > > > > > > > On Tue, 19 Oct 2021 14:27:02 +0100, > > > > Guo Ren <guoren@kernel.org> wrote: > > > > > > > > > > On Tue, Oct 19, 2021 at 6:18 PM Marc Zyngier <maz@kernel.org> wrote: > > > > > > > > > > > > On Tue, 19 Oct 2021 10:33:49 +0100, > > > > > > Guo Ren <guoren@kernel.org> wrote: > > > > > > > > > > > > > > If you have an 'automask' behavior and yet the HW doesn't record this > > > > > > > > in a separate bit, then you need to track this by yourself in the > > > > > > > > irq_eoi() callback instead. I guess that you would skip the write to > > > > > > > > the CLAIM register in this case, though I have no idea whether this > > > > > > > > breaks > > > > > > > > the HW interrupt state or not. > > > > > > > The problem is when enable bit is 0 for that irq_number, > > > > > > > "writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM)" wouldn't affect > > > > > > > the hw state machine. Then this irq would enter in ack state and no > > > > > > > continues irqs could come in. > > > > > > > > > > > > Really? This means that you cannot mask an interrupt while it is being > > > > > > handled? How great... > > > > > If the completion ID does not match an interrupt source that is > > > > > currently enabled for the target, the completion is silently ignored. > > > > > So, C9xx completion depends on enable-bit. > > > > > > > > Is that what the PLIC spec says? Or what your implementation does? I > > > > can understand that one implementation would be broken, but if the > > > > PLIC architecture itself is broken, that's far more concerning. > > > > > > Yes, we are dealing with a broken/non-compliant PLIC > > > implementation. > > > > > > The RISC-V PLIC spec defines a very different behaviour for the > > > interrupt claim (i.e. readl(claim)) and interrupt completion (i.e. > > > writel(claim)). The T-HEAD PLIC implementation does things > > > different from what the RISC-V PLIC spec says because it will > > > mask an interrupt upon interrupt claim whereas PLIC spec says > > > it should only clear the interrupt pending bit (not mask the interrupt). > > > > > > Quoting interrupt claim process (chapter 9) from PLIC spec: > > > "The PLIC can perform an interrupt claim by reading the claim/complete > > > register, which returns the ID of the highest priority pending interrupt or > > > zero if there is no pending interrupt. A successful claim will also atomically > > > clear the corresponding pending bit on the interrupt source." > > > > > > Refer, https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc > > > > That's not the point I'm making. According to Guo, the PLIC (any > > implementation of it) will ignore a write to claim on a masked > > interrupt. > > Yes, write to claim on a masked interrupt is certainly ignored but > read to claim does not automatically mask the interrupt. > > > > > If that's indeed correct, then a sequence such as: > > > > (1) irq = read(claim) > > This will return highest priority pending interrupt and clear the > pending bit as-per RISC-V PLIC spec. > > > (2) mask from the interrupt handler with the right flags so that it > > isn't done lazily > > (3) write(irq, claim) > > > > will result in an interrupt blocked in ack state (and probably no more > > interrupt for this CPU at this priority). That would be an interesting > > bug in the current code, but also a pretty bad architectural choice. > > The interrupt claim/completion is for each interrupt and not at CPU > level so if an interrupt is masked then only that interrupt is blocked > for all CPUs but other interrupts can still be raised.
Do you mean that another interrupt of the same priority will be able to be taken on *this* CPU, despite the completion being silently ignored?
M.
-- Without deviation from the norm, progress is not possible.
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