Messages in this thread | | | From | Anup Patel <> | Date | Wed, 20 Oct 2021 21:48:36 +0530 | Subject | Re: [PATCH V4 1/3] irqchip/sifive-plic: Add thead,c900-plic support |
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On Wed, Oct 20, 2021 at 8:29 PM Darius Rad <darius@bluespec.com> wrote: > > On Wed, Oct 20, 2021 at 10:19:06PM +0800, Guo Ren wrote: > > On Wed, Oct 20, 2021 at 9:34 PM Marc Zyngier <maz@kernel.org> wrote: > > > > > > On Tue, 19 Oct 2021 14:27:02 +0100, > > > Guo Ren <guoren@kernel.org> wrote: > > > > > > > > On Tue, Oct 19, 2021 at 6:18 PM Marc Zyngier <maz@kernel.org> wrote: > > > > > > > > > > On Tue, 19 Oct 2021 10:33:49 +0100, > > > > > Guo Ren <guoren@kernel.org> wrote: > > > > > > > > > > > > If you have an 'automask' behavior and yet the HW doesn't record this > > > > > > > in a separate bit, then you need to track this by yourself in the > > > > > > > irq_eoi() callback instead. I guess that you would skip the write to > > > > > > > the CLAIM register in this case, though I have no idea whether this > > > > > > > breaks > > > > > > > the HW interrupt state or not. > > > > > > The problem is when enable bit is 0 for that irq_number, > > > > > > "writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM)" wouldn't affect > > > > > > the hw state machine. Then this irq would enter in ack state and no > > > > > > continues irqs could come in. > > > > > > > > > > Really? This means that you cannot mask an interrupt while it is being > > > > > handled? How great... > > > > If the completion ID does not match an interrupt source that is > > > > currently enabled for the target, the completion is silently ignored. > > > > So, C9xx completion depends on enable-bit. > > > > > > Is that what the PLIC spec says? Or what your implementation does? I > > > can understand that one implementation would be broken, but if the > > > PLIC architecture itself is broken, that's far more concerning. > > > > Here is the description of Interrupt Completion in PLIC spec [1]: > > > > The PLIC signals it has completed executing an interrupt handler by > > writing the interrupt ID it received from the claim to the claim/complete > > register. The PLIC does not check whether the completion ID is the same > > as the last claim ID for that target. If the completion ID does not match > > an interrupt source that is currently enabled for the target, the > > ^^ ^^^^^^^^^ ^^^^^^^ > > completion is silently ignored. > > > > [1] https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc > > > > Did we misunderstand the PLIC spec? > > > > That clause sounds to me like it is due to the SiFive implementation, which > the RISC-V PLIC specification is based on. Since the PLIC spec is still a > draft I would expect it to change before release.
The SiFive PLIC has been adopted by various RISC-V platforms (including SiFive themselves). Almost all existing RISC-V boards have PLIC as the interrupt controller.
Considering the wide usage of PLIC across existing platforms, the RISC-V International has adopted it as an official RISC-V non-ISA spec. Of course, the RISC-V PLIC spec needs to follow the process for RISC-V non-ISA spec but changing the RISC-V PLIC spec now would mean all existing RISC-V platforms will become non-compliant.
The RISC-V AIA spec is intended to replace the RISC-V PLIC spec as the new interrupt controller spec for future RISC-V platforms.
Regards, Anup
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