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    Subject[PATCH v14 05/11] PCI: kirin: give more time for PERST# reset to finish
    Date
    Before code refactor, the PERST# signals were sent at the
    end of the power_on logic. Then, the PCI core would probe for
    the buses and add them.

    The new logic changed it to send PERST# signals during
    add_bus operation. That altered the timings.

    Also, HiKey 970 require a little more waiting time for
    the PCI bridge - which is outside the SoC - to finish
    the PERST# reset, and then initialize the eye diagram.

    So, increase the waiting time for the PERST# signals to
    what's required for it to also work with HiKey 970.

    Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
    ---

    See [PATCH v14 00/11] at: https://lore.kernel.org/all/cover.1634622716.git.mchehab+huawei@kernel.org/

    drivers/pci/controller/dwc/pcie-kirin.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c
    index de375795a3b8..bc329673632a 100644
    --- a/drivers/pci/controller/dwc/pcie-kirin.c
    +++ b/drivers/pci/controller/dwc/pcie-kirin.c
    @@ -113,7 +113,7 @@ struct kirin_pcie {
    #define CRGCTRL_PCIE_ASSERT_BIT 0x8c000000

    /* Time for delay */
    -#define REF_2_PERST_MIN 20000
    +#define REF_2_PERST_MIN 21000
    #define REF_2_PERST_MAX 25000
    #define PERST_2_ACCESS_MIN 10000
    #define PERST_2_ACCESS_MAX 12000
    --
    2.31.1
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