Messages in this thread | | | Date | Tue, 19 Oct 2021 12:02:34 +0100 | From | Will Deacon <> | Subject | Re: [PATCH v5 03/15] arm64: errata: Add workaround for TSB flush failures |
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On Thu, Oct 14, 2021 at 11:31:13PM +0100, Suzuki K Poulose wrote: > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c > index ccd757373f36..bdbeac75ead6 100644 > --- a/arch/arm64/kernel/cpu_errata.c > +++ b/arch/arm64/kernel/cpu_errata.c > @@ -352,6 +352,18 @@ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = { > }; > #endif /* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */ > > +#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE > +static const struct midr_range tsb_flush_fail_cpus[] = { > +#ifdef CONFIG_ARM64_ERRATUM_2067961 > + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), > +#endif > +#ifdef CONFIG_ARM64_ERRATUM_2054223 > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), > +#endif > + {}, > +}; > +#endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */ > + > const struct arm64_cpu_capabilities arm64_errata[] = { > #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE > { > @@ -558,6 +570,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { > .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, > CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus), > }, > +#endif > +#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILRE
You still haven't fixed this typo...
Seriously, I get compile warnings from this -- are you not seeing them?
Will
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