Messages in this thread Patch in this message | | | From | Smita Koralahalli <> | Subject | [PATCH v2 3/5] x86/mce: Use mca_msr_reg() in prepare_msrs() | Date | Tue, 19 Oct 2021 18:36:39 -0500 |
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Replace MCx_{STATUS, ADDR, MISC} macros with mca_msr_reg().
Also, restructure the code to avoid multiple initializations for MCA registers. SMCA machines define a different set of MSRs for MCA registers and mca_msr_reg() returns the proper MSR address for SMCA and legacy processors.
Initialize MCA_MISC and MCA_SYND registers at the end after initializing MCx_{STATUS, DESTAT} which is further explained in the next patch.
Make mca_msr_reg() exportable in order to be accessible from mce-inject module.
Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> --- v2: Replaced msr_ops -> mca_msr_reg(). --- arch/x86/kernel/cpu/mce/core.c | 1 + arch/x86/kernel/cpu/mce/inject.c | 27 +++++++++++++-------------- 2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 6ed365337a3b..fb4d8ac1cb4f 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -194,6 +194,7 @@ u32 mca_msr_reg(int bank, enum mca_msr reg) return 0; } +EXPORT_SYMBOL_GPL(mca_msr_reg); static void __print_mce(struct mce *m) { diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inject.c index a993dc3d0333..40d0bebe0cd2 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -461,22 +461,21 @@ static void prepare_msrs(void *info) wrmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); - if (boot_cpu_has(X86_FEATURE_SMCA)) { - if (m.inject_flags == DFR_INT_INJ) { - wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(b), m.status); - wrmsrl(MSR_AMD64_SMCA_MCx_DEADDR(b), m.addr); - } else { - wrmsrl(MSR_AMD64_SMCA_MCx_STATUS(b), m.status); - wrmsrl(MSR_AMD64_SMCA_MCx_ADDR(b), m.addr); - } + if (boot_cpu_has(X86_FEATURE_SMCA) && + m.inject_flags == DFR_INT_INJ) { + wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(b), m.status); + wrmsrl(MSR_AMD64_SMCA_MCx_DEADDR(b), m.addr); + goto out; + } + + wrmsrl(mca_msr_reg(b, MCA_STATUS), m.status); + wrmsrl(mca_msr_reg(b, MCA_ADDR), m.addr); - wrmsrl(MSR_AMD64_SMCA_MCx_MISC(b), m.misc); +out: + wrmsrl(mca_msr_reg(b, MCA_MISC), m.misc); + + if (boot_cpu_has(X86_FEATURE_SMCA)) wrmsrl(MSR_AMD64_SMCA_MCx_SYND(b), m.synd); - } else { - wrmsrl(MSR_IA32_MCx_STATUS(b), m.status); - wrmsrl(MSR_IA32_MCx_ADDR(b), m.addr); - wrmsrl(MSR_IA32_MCx_MISC(b), m.misc); - } } static void do_inject(void) -- 2.17.1
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