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Subject[PATCH] riscv: fix misalgned trap vector base address
Date
* The trap vector marked by label .Lsecondary_park should align on a
4-byte boundary. If not, CSR_TVEC may be set to an incorrect address.
* This bug is introduced at commit e011995e826f8 ("RISC-V: Move relocate
and few other functions out of __init").
* This bug is exposed with an educational emualtor.

Signed-off-by: Chen Lu <181250012@smail.nju.edu.cn>
---
arch/riscv/kernel/head.S | 1 +
1 file changed, 1 insertion(+)

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index fce5184b22c3..52c5ff9804c5 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -193,6 +193,7 @@ setup_trap_vector:
csrw CSR_SCRATCH, zero
ret

+.align 2
.Lsecondary_park:
/* We lack SMP support or have too many harts, so park this hart */
wfi
--
2.30.2


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