Messages in this thread Patch in this message | | | From | Martin Blumenstingl <> | Date | Thu, 14 Oct 2021 23:34:54 +0200 | Subject | Re: [PATCH v1 1/6] clk: divider: Implement and wire up .determine_rate by default |
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On Thu, Oct 14, 2021 at 2:11 PM Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote: [...] > > Reverting this commit makes it work again: Unless there is a quick and > > obvious fix for that, I guess this should be done for 5.15 - even if the > > real issue is somewhere else. > Reverting this patch is fine from the Amlogic SoC point of view. > The main goal was to clean up / improve the CCF code. > Nothing (that I am aware of) is going to break in Amlogic land if we > revert this. Unfortunately only now I realized that reverting this patch would also require reverting the other five patches in this series (since they depend on this one). For this reason I propose changing the order of the checks in clk-composite.c - see the attached patch (which I can send as a proper one once agreed that this is the way to go forward)
Off-list Alex also suggested that I should use rate_ops.determine_rate if available. While I agree that this makes sense in general my plan is to do this in a follow-up patch. Changing the order of the conditions is needed anyways and it *should* fix the issue reported here (but I have no way of testing that unfortunately).
Alex, it would be great if you (or someone with Rockchip boards) could test the attached patch and let me know if it fixes the reported problem.
Best regards, Martin From b34cde2d9e1d8ecb2c775cbcad519933f63b84f9 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Date: Thu, 14 Oct 2021 14:16:22 +0200 Subject: [PATCH] clk: composite: Also consider .determine_rate for rate + mux composites
Commit 69a00fb3d69706 ("clk: divider: Implement and wire up .determine_rate by default") switches clk_divider_ops to implement .determine_rate by default. This breaks composite clocks with multiple parents because clk-composite.c does not use the special handling for mux + divider combinations anymore (that was restricted to rate clocks which only implement .round_rate, but not .determine_rate).
Alex reports: This breaks lot of clocks for Rockchip which intensively uses composites, i.e. those clocks will always stay at the initial parent, which in some cases is the XTAL clock and I strongly guess it is the same for other platforms, which use composite clocks having more than one parent (e.g. mediatek, ti ...)
Example (RK3399) clk_sdio is set (initialized) with XTAL (24 MHz) as parent in u-boot. It will always stay at this parent, even if the mmc driver sets a rate of 200 MHz (fails, as the nature of things), which should switch it to any of its possible parent PLLs defined in mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p (see clk-rk3399.c) - which never happens.
Restore the original behavior by changing the priority of the conditions inside clk-composite.c. Now the special rate + mux case (with rate_ops having a .round_rate - which is still the case for the default clk_divider_ops) is preferred over rate_ops which have .determine_rate defined (and not further considering the mux).
Fixes: 69a00fb3d69706 ("clk: divider: Implement and wire up .determine_rate by default") Reported-by: Alex Bee <knaerzche@gmail.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> --- drivers/clk/clk-composite.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index 0506046a5f4b..510a9965633b 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c @@ -58,11 +58,8 @@ static int clk_composite_determine_rate(struct clk_hw *hw, long rate; int i; - if (rate_hw && rate_ops && rate_ops->determine_rate) { - __clk_hw_set_clk(rate_hw, hw); - return rate_ops->determine_rate(rate_hw, req); - } else if (rate_hw && rate_ops && rate_ops->round_rate && - mux_hw && mux_ops && mux_ops->set_parent) { + if (rate_hw && rate_ops && rate_ops->round_rate && + mux_hw && mux_ops && mux_ops->set_parent) { req->best_parent_hw = NULL; if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) { @@ -107,6 +104,9 @@ static int clk_composite_determine_rate(struct clk_hw *hw, req->rate = best_rate; return 0; + } else if (rate_hw && rate_ops && rate_ops->determine_rate) { + __clk_hw_set_clk(rate_hw, hw); + return rate_ops->determine_rate(rate_hw, req); } else if (mux_hw && mux_ops && mux_ops->determine_rate) { __clk_hw_set_clk(mux_hw, hw); return mux_ops->determine_rate(mux_hw, req); -- 2.33.0
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