Messages in this thread | | | From | Huacai Chen <> | Subject | [PATCH V7 00/10] irqchip: Add LoongArch-related irqchip drivers | Date | Wed, 13 Oct 2021 12:27:02 +0800 |
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LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its boot protocol LoongArch-specific interrupt controllers (similar to APIC) are already added in the next revision of ACPI Specification (current revision is 6.4).
Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together with LS7A chipsets. The irq chips in LoongArch computers include CPUINTC (CPU Core Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller), PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are all controllers out of CPU (i.e., in chipsets). These controllers (in other words, irqchips) are linked in a hierarchy, and there are two models of hierarchy (legacy model and extended model).
Legacy IRQ model:
In this model, the IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go to LIOINTC, and then CPUINTC.
+---------------------------------------------+ | | | +-----+ +---------+ +-------+ | | | IPI | --> | CPUINTC | <-- | Timer | | | +-----+ +---------+ +-------+ | | ^ | | | | | +---------+ +-------+ | | | LIOINTC | <-- | UARTs | | | +---------+ +-------+ | | ^ | | | | | +-----------+ | | | HTVECINTC | | | +-----------+ | | ^ ^ | | | | | | +---------+ +---------+ | | | PCH-PIC | | PCH-MSI | | | +---------+ +---------+ | | ^ ^ ^ | | | | | | | +---------+ +---------+ +---------+ | | | PCH-LPC | | Devices | | Devices | | | +---------+ +---------+ +---------+ | | ^ | | | | | +---------+ | | | Devices | | | +---------+ | | | | | +---------------------------------------------+
Extended IRQ model:
In this model, the IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to to CPUINTC directly.
+--------------------------------------------------------+ | | | +-----+ +---------+ +-------+ | | | IPI | --> | CPUINTC | <-- | Timer | | | +-----+ +---------+ +-------+ | | ^ ^ | | | | | | +---------+ +---------+ +-------+ | | | EIOINTC | | LIOINTC | <-- | UARTs | | | +---------+ +---------+ +-------+ | | ^ ^ | | | | | | +---------+ +---------+ | | | PCH-PIC | | PCH-MSI | | | +---------+ +---------+ | | ^ ^ ^ | | | | | | | +---------+ +---------+ +---------+ | | | PCH-LPC | | Devices | | Devices | | | +---------+ +---------+ +---------+ | | ^ | | | | | +---------+ | | | Devices | | | +---------+ | | | | | +--------------------------------------------------------+
This patchset adds some irqchip drivers for LoongArch, it is preparing to add LoongArch support in mainline kernel, we can see a snapshot here: https://github.com/loongson/linux/tree/loongarch-next
Cross-compile tool chain to build kernel: https://github.com/loongson/build-tools/releases
Loongson and LoongArch documentations: https://github.com/loongson/LoongArch-Documentation
LoongArch-specific interrupt controllers: https://mantis.uefi.org/mantis/view.php?id=2203
LoongArch use ACPI, but ACPI tables cannot describe the hierarchy of irqchips, so we initilize the irqchip subsystem in this way (from arch code):
cpu_domain = loongarch_cpu_irq_init(); liointc_domain = liointc_acpi_init(cpu_domain, acpi_liointc); eiointc_domain = eiointc_acpi_init(cpu_domain, acpi_eiointc); pch_pic_domain = pch_pic_acpi_init(eiointc_domain, acpi_pchpic); pch_msi_domain = pch_msi_acpi_init(eiointc_domain, acpi_pchmsi);
Upstream irqchip init function return an irqdomain, and this domain will be used by downstream irqchips as their parent domains. For more infomation please refer: https://lore.kernel.org/linux-arch/20210927064300.624279-11-chenhuacai@loongson.cn/T/#u
Attention: CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described in Section 7.4 of "LoongArch Reference Manual, Vol 1"; LIOINTC is "Legacy I/O Interrupts" described in Section 11.1 of "Loongson 3A5000 Processor Reference Manual"; EIOINTC is "Extended I/O Interrupts" described in Section 11.2 of "Loongson 3A5000 Processor Reference Manual"; HTVECINTC is "HyperTransport Interrupts" described in Section 14.3 of "Loongson 3A5000 Processor Reference Manual"; PCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of "Loongson 7A1000 Bridge User Manual"; PCH-LPC is "LPC Interrupts" described in Section 24.3 of "Loongson 7A1000 Bridge User Manual".
V1 -> V2: 1, Remove queued patches; 2, Move common logic of DT/ACPI probing to common functions; 3, Split .suspend()/.resume() functions to separate patches.
V2 -> V3: 1, Fix a bug for loongson-pch-pic probe; 2, Some minor improvements for LPC controller.
V3 -> V4: 1, Rework the CPU interrupt controller driver; 2, Some minor improvements for other controllers.
V4 -> V5: 1, Add a description of LoonArch's IRQ model; 2, Support multiple EIOINTCs in one system; 3, Some minor improvements for other controllers.
V5 -> V6: 1, Attach a fwnode to CPUINTC irq domain; 2, Use raw spinlock instead of generic spinlock; 3, Improve the method of restoring EIOINTC state; 4, Update documentation, comments and commit messages.
V6 -> V7: 1, Fix build warnings reported by kernel test robot;
Huacai Chen: irqchip: Adjust Kconfig for Loongson. irqchip/loongson-pch-pic: Add ACPI init support. irqchip/loongson-pch-pic: Add suspend/resume support. irqchip/loongson-pch-msi: Add ACPI init support. irqchip/loongson-htvec: Add ACPI init support. irqchip/loongson-htvec: Add suspend/resume support. irqchip/loongson-liointc: Add ACPI init support. irqchip: Add LoongArch CPU interrupt controller support. irqchip: Add Loongson Extended I/O interrupt controller. irqchip: Add Loongson PCH LPC controller support.
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> --- drivers/irqchip/Kconfig | 37 +++- drivers/irqchip/Makefile | 3 + drivers/irqchip/irq-loongarch-cpu.c | 89 +++++++++ drivers/irqchip/irq-loongson-eiointc.c | 331 +++++++++++++++++++++++++++++++++ drivers/irqchip/irq-loongson-htvec.c | 142 ++++++++++---- drivers/irqchip/irq-loongson-liointc.c | 198 ++++++++++++-------- drivers/irqchip/irq-loongson-pch-lpc.c | 203 ++++++++++++++++++++ drivers/irqchip/irq-loongson-pch-msi.c | 119 +++++++----- drivers/irqchip/irq-loongson-pch-pic.c | 152 ++++++++++++--- include/linux/cpuhotplug.h | 1 + 10 files changed, 1087 insertions(+), 188 deletions(-) create mode 100644 drivers/irqchip/irq-loongarch-cpu.c create mode 100644 drivers/irqchip/irq-loongson-eiointc.c create mode 100644 drivers/irqchip/irq-loongson-pch-lpc.c -- 2.27.0
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