Messages in this thread | | | Date | Wed, 13 Oct 2021 23:08:34 +0200 | From | Peter Zijlstra <> | Subject | Re: [PATCH 5/9] x86/alternative: Handle Jcc __x86_indirect_thunk_\reg |
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On Wed, Oct 13, 2021 at 01:11:45PM -0700, Nick Desaulniers wrote:
> > + /* > > + * Convert: > > + * > > + * Jcc.d32 __x86_indirect_thunk_\reg > > + * > > + * into: > > + * > > + * Jncc.d8 1f > > + * jmp *%\reg > > + * nop > > + * 1: > > + */ > > + if (op == 0x0f && (insn->opcode.bytes[1] & 0xf0) == 0x80) { > > + cc = insn->opcode.bytes[1] & 0xf; > > + cc ^= 1; /* invert condition */ > > + > > + bytes[i++] = 0x70 + cc; /* Jcc.d8 */ > > + bytes[i++] = insn->length - 2; > > Isn't `insn->length - 2` always 4 (in this case)? We could avoid > computing that at runtime I suspect if we just hardcoded it.
Yeah, but I found this to be more expressive. The purpose is getting to the next instruction.
Also, if clang ever does instruction stuffing to hit alignment targets without extra nops (ISTR reading about such passes) this logic still works.
That is, I think you can prefix this with REX.W just to make a longer instruction.
> Either way, I've looked at the disassembly enough that this LGTM. > Thanks for the patch. > > Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Thanks!
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