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SubjectRe: [PATCH v3 2/8] net: phy: Add 10-BaseT1L registers
On Mon, Oct 11, 2021 at 05:22:09PM +0300, alexandru.tachici@analog.com wrote:
> From: Alexandru Tachici <alexandru.tachici@analog.com>
>
> The 802.3gc specification defines the 10-BaseT1L link
> mode for ethernet trafic on twisted wire pair.
>
> PMA status register can be used to detect if the phy supports
> 2.4 V TX level and PCS control register can be used to
> enable/disable PCS level loopback.
>
> Signed-off-by: Alexandru Tachici <alexandru.tachici@analog.com>

Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Thank you!

Question on maintainers: IEEE 802.3 spec, documents register bits in the
little-endian order. In the mdio.h we use big-endian, it makes
comparison with the spec a bit more challenging. May be we should fix
it?

Regards,
Oleksij

> ---
> include/uapi/linux/mdio.h | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h
> index bdf77dffa5a4..8ae82fe3aece 100644
> --- a/include/uapi/linux/mdio.h
> +++ b/include/uapi/linux/mdio.h
> @@ -65,6 +65,8 @@
> #define MDIO_PCS_10GBRT_STAT2 33 /* 10GBASE-R/-T PCS status 2 */
> #define MDIO_AN_10GBT_CTRL 32 /* 10GBASE-T auto-negotiation control */
> #define MDIO_AN_10GBT_STAT 33 /* 10GBASE-T auto-negotiation status */
> +#define MDIO_PMA_10T1L_STAT 2295 /* 10BASE-T1L PMA status */
> +#define MDIO_PCS_10T1L_CTRL 2278 /* 10BASE-T1L PCS control */
>
> /* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */
> #define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */
> @@ -262,6 +264,20 @@
> #define MDIO_AN_10GBT_STAT_MS 0x4000 /* Master/slave config */
> #define MDIO_AN_10GBT_STAT_MSFLT 0x8000 /* Master/slave config fault */
>
> +/* 10BASE-T1L PMA status register. */
> +#define MDIO_PMA_10T1L_STAT_LINK 0x0001 /* PMA receive link up */
> +#define MDIO_PMA_10T1L_STAT_FAULT 0x0002 /* Fault condition detected */
> +#define MDIO_PMA_10T1L_STAT_POLARITY 0x0004 /* Receive polarity is reversed */
> +#define MDIO_PMA_10T1L_STAT_RECV_FAULT 0x0200 /* Able to detect fault on receive path */
> +#define MDIO_PMA_10T1L_STAT_EEE 0x0400 /* PHY has EEE ability */
> +#define MDIO_PMA_10T1L_STAT_LOW_POWER 0x0800 /* PMA has low-power ability */
> +#define MDIO_PMA_10T1L_STAT_2V4_ABLE 0x1000 /* PHY has 2.4 Vpp operating mode ability */
> +#define MDIO_PMA_10T1L_STAT_LB_ABLE 0x2000 /* PHY has loopback ability */
> +
> +/* 10BASE-T1L PCS control register. */
> +#define MDIO_PCS_10T1L_CTRL_LB 0x4000 /* Enable PCS level loopback mode */
> +#define MDIO_PCS_10T1L_CTRL_RESET 0x8000 /* PCS reset */
> +
> /* EEE Supported/Advertisement/LP Advertisement registers.
> *
> * EEE capability Register (3.20), Advertisement (7.60) and
> --
> 2.25.1



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