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    Subject[PATCH v1 09/16] reset: starfive-jh7100: Add StarFive JH7100 reset driver
    Date
    Add a driver for the StarFive JH7100 reset controller.

    Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
    ---
    MAINTAINERS | 7 ++
    drivers/reset/Kconfig | 8 ++
    drivers/reset/Makefile | 1 +
    drivers/reset/reset-starfive-jh7100.c | 164 ++++++++++++++++++++++++++
    4 files changed, 180 insertions(+)
    create mode 100644 drivers/reset/reset-starfive-jh7100.c

    diff --git a/MAINTAINERS b/MAINTAINERS
    index d2b95b96f0ec..f7883377895e 100644
    --- a/MAINTAINERS
    +++ b/MAINTAINERS
    @@ -17854,6 +17854,13 @@ F: Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml
    F: drivers/clk/starfive/clk-starfive-jh7100.c
    F: include/dt-bindings/clock/starfive-jh7100.h

    +STARFIVE JH7100 RESET CONTROLLER DRIVER
    +M: Emil Renner Berthing <kernel@esmil.dk>
    +S: Maintained
    +F: Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
    +F: drivers/reset/reset-starfive-jh7100.c
    +F: include/dt-bindings/reset/starfive-jh7100.h
    +
    STATIC BRANCH/CALL
    M: Peter Zijlstra <peterz@infradead.org>
    M: Josh Poimboeuf <jpoimboe@redhat.com>
    diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
    index be799a5abf8a..8345521744b3 100644
    --- a/drivers/reset/Kconfig
    +++ b/drivers/reset/Kconfig
    @@ -92,6 +92,14 @@ config RESET_INTEL_GW
    Say Y to control the reset signals provided by reset controller.
    Otherwise, say N.

    +config RESET_STARFIVE_JH7100
    + bool "StarFive JH7100 Reset Driver"
    + depends on SOC_STARFIVE || COMPILE_TEST
    + depends on OF
    + default SOC_STARFIVE
    + help
    + This enables the reset controller driver for the StarFive JH7100 SoC.
    +
    config RESET_K210
    bool "Reset controller driver for Canaan Kendryte K210 SoC"
    depends on (SOC_CANAAN || COMPILE_TEST) && OF
    diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
    index 21d46d8869ff..021eff3525de 100644
    --- a/drivers/reset/Makefile
    +++ b/drivers/reset/Makefile
    @@ -13,6 +13,7 @@ obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o
    obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
    obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
    obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
    +obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
    obj-$(CONFIG_RESET_K210) += reset-k210.o
    obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
    obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
    diff --git a/drivers/reset/reset-starfive-jh7100.c b/drivers/reset/reset-starfive-jh7100.c
    new file mode 100644
    index 000000000000..26bc5b59c1f3
    --- /dev/null
    +++ b/drivers/reset/reset-starfive-jh7100.c
    @@ -0,0 +1,164 @@
    +// SPDX-License-Identifier: GPL-2.0-or-later
    +/*
    + * Reset driver for the StarFive JH7100 SoC
    + *
    + * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
    + *
    + */
    +
    +#include <linux/io.h>
    +#include <linux/of_device.h>
    +#include <linux/platform_device.h>
    +#include <linux/reset-controller.h>
    +#include <linux/spinlock.h>
    +
    +#include <dt-bindings/reset/starfive-jh7100.h>
    +
    +/* register offsets */
    +#define JH7100_RESET_ASSERT0 0x00
    +#define JH7100_RESET_ASSERT1 0x04
    +#define JH7100_RESET_ASSERT2 0x08
    +#define JH7100_RESET_ASSERT3 0x0c
    +#define JH7100_RESET_STATUS0 0x10
    +#define JH7100_RESET_STATUS1 0x14
    +#define JH7100_RESET_STATUS2 0x18
    +#define JH7100_RESET_STATUS3 0x1c
    +
    +struct jh7100_reset {
    + struct reset_controller_dev rcdev;
    + /* protect registers against overlapping read-modify-write */
    + spinlock_t lock;
    + void __iomem *base;
    +};
    +
    +static inline struct jh7100_reset *
    +jh7100_reset_from(struct reset_controller_dev *rcdev)
    +{
    + return container_of(rcdev, struct jh7100_reset, rcdev);
    +}
    +
    +static const u32 jh7100_reset_asserted[4] = {
    + BIT(JH7100_RST_U74 % 32) |
    + BIT(JH7100_RST_VP6_DRESET % 32) |
    + BIT(JH7100_RST_VP6_BRESET % 32),
    +
    + BIT(JH7100_RST_HIFI4_DRESET % 32) |
    + BIT(JH7100_RST_HIFI4_BRESET % 32),
    +
    + BIT_MASK(JH7100_RST_E24 % 32)
    +};
    +
    +static int jh7100_reset_update(struct reset_controller_dev *rcdev,
    + unsigned long id, bool assert)
    +{
    + struct jh7100_reset *data = jh7100_reset_from(rcdev);
    + unsigned long offset = id / 32;
    + void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + 4 * offset;
    + void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + 4 * offset;
    + u32 mask = BIT(id % 32);
    + u32 done = jh7100_reset_asserted[offset] & mask;
    + unsigned long flags;
    + u32 value;
    +
    + if (!assert)
    + done ^= mask;
    +
    + spin_lock_irqsave(&data->lock, flags);
    +
    + value = readl(reg_assert);
    + if (assert)
    + value |= mask;
    + else
    + value &= ~mask;
    + writel(value, reg_assert);
    +
    + do {
    + value = readl(reg_status) & mask;
    + } while (value != done);
    +
    + spin_unlock_irqrestore(&data->lock, flags);
    + return 0;
    +}
    +
    +static int jh7100_reset_assert(struct reset_controller_dev *rcdev,
    + unsigned long id)
    +{
    + dev_dbg(rcdev->dev, "assert(%lu)\n", id);
    + return jh7100_reset_update(rcdev, id, true);
    +}
    +
    +static int jh7100_reset_deassert(struct reset_controller_dev *rcdev,
    + unsigned long id)
    +{
    + dev_dbg(rcdev->dev, "deassert(%lu)\n", id);
    + return jh7100_reset_update(rcdev, id, false);
    +}
    +
    +static int jh7100_reset_reset(struct reset_controller_dev *rcdev,
    + unsigned long id)
    +{
    + int ret;
    +
    + dev_dbg(rcdev->dev, "reset(%lu)\n", id);
    + ret = jh7100_reset_assert(rcdev, id);
    + if (ret)
    + return ret;
    +
    + return jh7100_reset_deassert(rcdev, id);
    +}
    +
    +static int jh7100_reset_status(struct reset_controller_dev *rcdev,
    + unsigned long id)
    +{
    + struct jh7100_reset *data = jh7100_reset_from(rcdev);
    + unsigned long offset = id / 32;
    + void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + 4 * offset;
    + u32 mask = BIT(id % 32);
    + u32 value = (readl(reg_status) ^ jh7100_reset_asserted[offset]) & mask;
    +
    + dev_dbg(rcdev->dev, "status(%lu) = %d\n", id, !value);
    + return !value;
    +}
    +
    +static const struct reset_control_ops jh7100_reset_ops = {
    + .assert = jh7100_reset_assert,
    + .deassert = jh7100_reset_deassert,
    + .reset = jh7100_reset_reset,
    + .status = jh7100_reset_status,
    +};
    +
    +static int jh7100_reset_probe(struct platform_device *pdev)
    +{
    + struct jh7100_reset *data;
    +
    + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
    + if (!data)
    + return -ENOMEM;
    +
    + data->base = devm_platform_ioremap_resource(pdev, 0);
    + if (IS_ERR(data->base))
    + return PTR_ERR(data->base);
    +
    + data->rcdev.ops = &jh7100_reset_ops;
    + data->rcdev.owner = THIS_MODULE;
    + data->rcdev.nr_resets = JH7100_RSTN_END;
    + data->rcdev.dev = &pdev->dev;
    + data->rcdev.of_node = pdev->dev.of_node;
    + spin_lock_init(&data->lock);
    +
    + return devm_reset_controller_register(&pdev->dev, &data->rcdev);
    +}
    +
    +static const struct of_device_id jh7100_reset_dt_ids[] = {
    + { .compatible = "starfive,jh7100-reset" },
    + { /* sentinel */ },
    +};
    +
    +static struct platform_driver jh7100_reset_driver = {
    + .probe = jh7100_reset_probe,
    + .driver = {
    + .name = "jh7100-reset",
    + .of_match_table = jh7100_reset_dt_ids,
    + },
    +};
    +builtin_platform_driver(jh7100_reset_driver);
    --
    2.33.0
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