Messages in this thread | | | From | Alex Deucher <> | Date | Mon, 11 Oct 2021 10:32:15 -0400 | Subject | Re: `AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT=y` causes AMDGPU to fail on Ryzen: amdgpu: SME is not compatible with RAVEN |
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On Mon, Oct 11, 2021 at 10:21 AM Paul Menzel <pmenzel@molgen.mpg.de> wrote: > > Dear Tom, > > > Am 11.10.21 um 15:58 schrieb Tom Lendacky: > > On 10/11/21 8:52 AM, Paul Menzel wrote: > > >> Am 11.10.21 um 15:27 schrieb Tom Lendacky: > >>> On 10/11/21 8:11 AM, Borislav Petkov wrote: > >>>> On Mon, Oct 11, 2021 at 03:05:33PM +0200, Paul Menzel wrote: > >>>>> I think, the IOMMU is enabled on the MSI B350M MORTAR, but > >>>>> otherwise, yes > >>>>> this looks fine. The help text could also be updated to mention > >>>>> problems > >>>>> with AMD Raven devices. > >>>> > >>>> This is not only about Raven GPUs but, as Alex explained, pretty much > >>>> about every device which doesn't support a 48 bit DMA mask. I'll expand > >>>> that aspect in the changelog. > >>> > >>> In general, non-GPU devices that don't support a 48-bit DMA mask work > >>> fine (assuming they have set their DMA mask appropriately). It really > >>> depends on whether SWIOTLB will be able to satisfy the memory > >>> requirements of the driver when the IOMMU is not enabled or in > >>> passthrough mode. Since GPU devices need/use a lot of memory, that > >>> becomes a problem. > >> > >> How can I check that? > > > > How can you check what? 32-bit DMA devices? GPUs? I need a bit more > > information... > > How can I check, why MEM_ENCRYPT is not working on my device despite the > IOMMU being enabled.
I think there are several potential problem cases:
1. Device is in passthrough mode in the IOMMU and the device has a limited DMA mask. This could be due to a hardware requirements (e.g., IOMMUv2 functionality) or a hardware/platform requirements (e.g., ACPI IOMMU tables define passthrough for a specific device or memory region). This is the case for Raven.
2. Device driver bug (e.g., driver not using the DMA API properly)
Alex
> > > Kind regards, > > Paul
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