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    Subject[PATCH 5.14 017/151] drm/amd/display: Fix DCN3 B0 DP Alt Mapping
    Date
    From: Liu, Zhan <Zhan.Liu@amd.com>

    commit 2fe9a0e1173f4805669e7af34ea25af835274426 upstream.

    [Why]
    DCN3 B0 has a mux, which redirects PHYC and PHYD to PHYF and PHYG.

    [How]
    Fix DIG mapping.

    Reviewed-by: Charlene Liu <charlene.liu@amd.com>
    Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
    Signed-off-by: Zhan Liu <Zhan.Liu@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Cc: stable@vger.kernel.org
    (cherry picked from commit 4b7786d87fb3adf3e534c4f1e4f824d8700b786b)
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 6 ++++++
    1 file changed, 6 insertions(+)

    --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
    +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
    @@ -1284,6 +1284,12 @@ static struct stream_encoder *dcn31_stre
    if (!enc1 || !vpg || !afmt)
    return NULL;

    + if (ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
    + ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
    + if ((eng_id == ENGINE_ID_DIGC) || (eng_id == ENGINE_ID_DIGD))
    + eng_id = eng_id + 3; // For B0 only. C->F, D->G.
    + }
    +
    dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
    eng_id, vpg, afmt,
    &stream_enc_regs[eng_id],

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