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    Subject[PATCH 5.14 016/151] drm/amd/display: Fix detection of 4 lane for DPALT
    Date
    From: Hansen <Hansen.Dsouza@amd.com>

    commit 5a1fef027846e7635b9d320b2cc0b416fd11a3be upstream.

    [Why]
    DPALT detection for B0 PHY has its own set of RDPCSPIPE registers

    [How]
    Use RDPCSPIPE registers to detect if DPALT lane is 4 lane

    Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
    Acked-by: Solomon Chiu <solomon.chiu@amd.com>
    Signed-off-by: Hansen <Hansen.Dsouza@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Cc: stable@vger.kernel.org
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c | 33 +++++++++-
    drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h | 3
    2 files changed, 35 insertions(+), 1 deletion(-)

    --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
    +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
    @@ -63,6 +63,10 @@
    #define AUX_REG_WRITE(reg_name, val) \
    dm_write_reg(CTX, AUX_REG(reg_name), val)

    +#ifndef MIN
    +#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
    +#endif
    +
    void dcn31_link_encoder_set_dio_phy_mux(
    struct link_encoder *enc,
    enum encoder_type_select sel,
    @@ -217,7 +221,7 @@ static const struct link_encoder_funcs d
    .get_dig_frontend = dcn10_get_dig_frontend,
    .get_dig_mode = dcn10_get_dig_mode,
    .is_in_alt_mode = dcn31_link_encoder_is_in_alt_mode,
    - .get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
    + .get_max_link_cap = dcn31_link_encoder_get_max_link_cap,
    .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,
    };

    @@ -435,3 +439,30 @@ bool dcn31_link_encoder_is_in_alt_mode(s

    return is_usb_c_alt_mode;
    }
    +
    +void dcn31_link_encoder_get_max_link_cap(struct link_encoder *enc,
    + struct dc_link_settings *link_settings)
    +{
    + struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
    + uint32_t is_in_usb_c_dp4_mode = 0;
    +
    + dcn10_link_encoder_get_max_link_cap(enc, link_settings);
    +
    + /* in usb c dp2 mode, max lane count is 2 */
    + if (enc->funcs->is_in_alt_mode && enc->funcs->is_in_alt_mode(enc)) {
    + if (enc->ctx->asic_id.hw_internal_rev != YELLOW_CARP_B0) {
    + // [Note] no need to check hw_internal_rev once phy mux selection is ready
    + REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
    + } else {
    + if ((enc10->base.transmitter == TRANSMITTER_UNIPHY_A)
    + || (enc10->base.transmitter == TRANSMITTER_UNIPHY_B)
    + || (enc10->base.transmitter == TRANSMITTER_UNIPHY_E)) {
    + REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
    + } else {
    + REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
    + }
    + }
    + if (!is_in_usb_c_dp4_mode)
    + link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count);
    + }
    +}
    --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h
    +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h
    @@ -252,4 +252,7 @@ void dcn31_link_encoder_disable_output(
    bool dcn31_link_encoder_is_in_alt_mode(
    struct link_encoder *enc);

    +void dcn31_link_encoder_get_max_link_cap(struct link_encoder *enc,
    + struct dc_link_settings *link_settings);
    +
    #endif /* __DC_LINK_ENCODER__DCN31_H__ */

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