Messages in this thread | | | Date | Mon, 11 Oct 2021 11:18:52 +0100 | From | Will Deacon <> | Subject | Re: [PATCH v3 15/16] arm64: errata: Advertise the workaround for TSB flush failures |
| |
On Fri, Oct 08, 2021 at 07:29:05PM +0100, Suzuki K Poulose wrote: > Advertise the workaround for the TSB flush failures via > Kconfig entries. > > Cc: Will Deacon <will@kernel.org> > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Mathieu Poirier <mathieu.poirier@linaro.org> > Cc: Anshuman Khandual <anshuman.khandual@arm.com> > Cc: Marc Zyngier <maz@kernel.org> > Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> > Acked-by: Catalin Marinas <catalin.marinas@arm.com> > Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> > --- > Changes since previous: > - Split the Kconfig/erratum updates to keep the conflicts > minimal with the other Kconfig updates in TRBE errata > I have retained the tags > --- > Documentation/arm64/silicon-errata.rst | 4 ++++ > arch/arm64/Kconfig | 31 ++++++++++++++++++++++++++ > 2 files changed, 35 insertions(+) > > diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst > index 2f99229d993c..569a92411dcd 100644 > --- a/Documentation/arm64/silicon-errata.rst > +++ b/Documentation/arm64/silicon-errata.rst > @@ -94,6 +94,8 @@ stable kernels. > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 | > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Neoverse-N1 | #1349291 | N/A | > @@ -102,6 +104,8 @@ stable kernels. > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Neoverse-N2 | #2139208 | ARM64_ERRATUM_2139208 | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Neoverse-N2 | #2067961 | ARM64_ERRATUM_2067961 | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | MMU-500 | #841119,826419 | N/A | > +----------------+-----------------+-----------------+-----------------------------+ > +----------------+-----------------+-----------------+-----------------------------+ > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index eac4030322df..0764774e12bb 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -705,6 +705,37 @@ config ARM64_ERRATUM_2139208 > > If unsure, say Y. > > +config ARM64_WORKAROUND_TSB_FLUSH_FAILURE > + bool > + > +config ARM64_ERRATUM_2054223 > + bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" > + default y > + help > + Enable workaround for ARM Cortex-A710 erratum 2054223 > + > + Affected cores may fail to flush the trace data on a TSB instruction, when > + the PE is in trace prohibited state. This will cause losing a few bytes > + of the trace cached. > + > + Workaround is to issue two TSB consecutively on affected cores. > + > + If unsure, say Y. > + > +config ARM64_ERRATUM_2067961 > + bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" > + default y > + help > + Enable workaround for ARM Neoverse-N2 erratum 2067961 > + > + Affected cores may fail to flush the trace data on a TSB instruction, when > + the PE is in trace prohibited state. This will cause losing a few bytes > + of the trace cached. > + > + Workaround is to issue two TSB consecutively on affected cores. > + > + If unsure, say Y.
Shouldn't these two be selecting the workaround?
Will
| |